CMOS Analog Switch Gate Drive for High-Voltage Signal Integrity
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Solution Overview
Problem
Conventional analog switch circuits using N-type and P-type MOSFETs in parallel face signal distortion issues at high voltages, and the use of high gate withstand voltage transistors increases costs without ensuring the transistors' reliability.
Innovation Solution
An analog switch circuit design where N-type and P-type MOSFETs are arranged in parallel, with specific gate drive circuits controlling the gate-source voltages to keep them within the gate withstand voltage range, even at voltages higher than the general gate withstand voltage, using a configuration where the source and drain terminals of both MOSFETs are connected, and the gate drive signals are adjusted based on an enable and control signal to maintain safe voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors with high gate withstand voltage are used to operate at voltages higher than general gate withstand voltage, then the analog switch can operate at high voltages, but manufacturing costs increase
Solution Approach 1:
The patent changes the voltage parameters dynamically by using separate gate drive circuits that adjust gate-source voltages based on the analog input voltage level. When Vin is high, the NMOS gate voltage is reduced and PMOS gate voltage is increased to keep |Vgs| within safe limits, enabling operation at voltages higher than the transistor's rated gate withstand voltage
Solution Approach 2:
The patent introduces gate drive circuits as intermediary components between the analog input and the MOSFET gates. These circuits actively control and limit the gate-source voltages, acting as a protective mediator that enables high-voltage operation without exceeding transistor gate ratings
2Reliability
If the gate-source voltage exceeds the gate withstand voltage, then the transistor can handle higher voltages, but the oxide film breaks and reliability decreases
Solution Approach 1:
The gate drive circuits perform preliminary action by pre-calculating and setting appropriate gate-source voltages before the analog switch operates at high voltages. The circuits ensure that gate voltages are adjusted in advance to prevent oxide film breakdown while maintaining voltage handling capability
Solution Approach 2:
The gate drive circuits use feedback from the analog input voltage to dynamically adjust gate-source voltages. By monitoring Vin and adjusting Vg_n and Vg_p accordingly, the system maintains |Vgs| within safe limits while adapting to different input voltage levels, preventing oxide film damage
3Manufacturing precision
If N-type MOSFET is used as analog switch, then high voltage side of input signal is distorted in output signal, but using P-type MOSFET causes low voltage side distortion
Solution Approach 1:
The patent merges NMOS and PMOS transistors in a complementary configuration where both are controlled by separate gate drive circuits. This combination allows the circuit to leverage the strengths of both transistor types while compensating for their individual weaknesses across the full voltage range
Data Source
AI summary
An analog switch circuit of an embodiment includes a CMOS analog switch, a first gate drive circuit, and a second gate drive circuit, a gate operating withstand voltage of the CMOS analog switch being VGT, an enable signal and a control signal being inputted to the first gate drive circuit and the second gate drive circuit. Assuming that VGT<VSH≤(2×VGT), in a case where the enable signal is 0, the second gate drive circuit outputs a signal of voltage (VSH/2) to a gate terminal of a PMOS when the control signal is 0, and the first gate drive circuit outputs a signal of voltage (VSH/2) to a gate terminal of an NMOS when the control signal is 1.