CMOS Switched Capacitor Circuit for Linear Equivalent Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Prior art switched capacitors exhibit nonlinearity in their equivalent capacitance due to parasitic capacitors, which is undesirable in many applications.
Innovation Solution
A switched capacitor circuit design incorporating N-type and P-type switches, transmission gates, and specific resistor configurations to maintain linearity in both states, utilizing complementary metal oxide semiconductor (CMOS) transistors and resistors to control capacitance effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single NMOS transistor is used as the switch, then the circuit is simple, but the equivalent capacitance becomes nonlinear due to parasitic capacitors
Solution Approach 1:
The single NMOS switch is segmented into multiple components: an NMOS transistor, a PMOS transistor, and a transmission gate. Each component's parasitic capacitance is separated and can be independently managed. The transmission gate is further segmented into parallel NMOS and PMOS transistors whose nonlinearities cancel each other.
Solution Approach 2:
The patent applies counterweight by using complementary transistors (NMOS and PMOS) with opposite characteristics. The nonlinear parasitic capacitance of the NMOS transistor is counterbalanced by the nonlinear parasitic capacitance of the PMOS transistor, achieving linear equivalent capacitance through cancellation of opposing nonlinear effects.
2Ease of manufacture
If parasitic capacitors are present in the switch, then the switch can be implemented with standard transistors, but the equivalent capacitance in the second state becomes nonlinear
Solution Approach 1:
The patent converts the harmful nonlinear parasitic capacitors into a beneficial configuration. Instead of trying to eliminate the parasitic capacitances, the design uses them intentionally by placing complementary transistors in parallel so their nonlinearities cancel out, transforming a defect into a feature that achieves linearity.
3Manufacturing precision
If complementary transistors with different sizes are used, then linearity is improved, but the device complexity increases
Solution Approach 1:
The patent applies local quality by making the NMOS and PMOS transistors have different sizes optimized for their specific roles. The width-to-length ratios are carefully selected to balance the parasitic capacitances locally at each transistor, achieving overall linearity through localized optimization rather than uniform design.
Data Source
AI summary
A circuit and method are provided. The method couples a first bias signal to a first internal node via a first resistor, couples a second bias signal to a second internal node via a second resistor, couples the first internal node to a ground node via a N-type switch, couples the second internal node to a power supply node via a P-type switch. The method further couples the first internal node to the second internal node via a transmission gate, couples a terminal to the first internal node via a first capacitor, and couples the terminal to the second internal node via a second capacitor.