CMOS Synapse Circuit Using Constant Current Source
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Solution Overview
Problem
Current neural system implementations face challenges in achieving area efficiency and low power consumption due to the high number of neurons and synapses, with existing methods consuming excessive power and only allowing for one type of synaptic connection.
Innovation Solution
A synaptic electrical circuit using a constant electrical current source and a resistive divider to scale the current, enabling both excitatory and inhibitory connections while reducing power consumption and area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a fixed voltage is applied across a variable resistor to generate synaptic current, then the synaptic connection can be implemented, but power consumption becomes high
Solution Approach 1:
The patent changes the fundamental operating parameter from voltage-driven to current-driven operation. By using a constant current source instead of fixed voltage, the synaptic current is directly controlled by the resistance value, enabling both excitatory and inhibitory connections while maintaining low power consumption below 100 nW per synapse.
2Adaptability or versatility
If a fixed voltage across variable resistor is used, then synaptic connection is achieved, but only one type of connection (excitatory or inhibitory) can be implemented
Solution Approach 1:
The constant current source configuration provides universal functionality for both excitatory and inhibitory synaptic connections. By adjusting the resistance value, the circuit can generate positive currents for excitatory connections or negative currents for inhibitory connections, making a single circuit design applicable to all synapse types in the neural network.
3Duration of action of moving object
If hundreds of fF capacitance is used for neuron membrane simulation, then time constant close to biological systems is achieved, but area consumed by single neuron becomes large
Solution Approach 1:
The patent replaces the physical capacitor-based membrane model with an equivalent RC circuit implementation using standard on-chip resistors and capacitors. This substitution allows achieving the required 1 ms time constant using much smaller capacitance values (2-11 fF/μm2 density) by optimizing the resistance values, thereby reducing the area per neuron while maintaining biological fidelity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves low power consumption (less than 1.2 nW per synapse) and efficient area usage, allowing for both positive and negative synaptic weights, mimicking neural self-organization by enabling the establishment and removal of synaptic connections.
Implementation Method 1
a resistive divider to scale the constant electrical current to generate an output electrical current
Data Source
AI summary
Certain embodiments of the present disclosure support techniques for power efficient implementation of neuron synapses with positive and/or negative synaptic weights.