CMOS-Integrated Synaptic Array Structure With Low-Voltage Erase
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Solution Overview
Problem
Conventional TFT devices face issues with large size and complex design of CMOS peripheral circuits due to the need for both positive and negative bias voltages, high power consumption during erase operations, and the Kink effect caused by accumulated holes, which are exacerbated by increased complexity and cost in fabrication processes.
Innovation Solution
A synaptic array structure integrating TFT-type synaptic devices and CMOS peripheral circuits on a semiconductor substrate with a semiconductor body between the source and drain, using a self-aligned TFT gate electrode and a curved semiconductor channel to reduce erase voltage and prevent the Kink effect, while sharing fabrication steps to minimize masks and processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMOS peripheral circuits are designed to implement both positive and negative bias voltages, then the voltage requirements are met, but the circuit size increases and design becomes more complicated
Solution Approach 1:
Instead of using CMOS circuits to generate negative voltage, the patent inverts the approach by using a P-type semiconductor body to naturally provide positive voltage during erase operations. This eliminates the need for complex CMOS voltage generation circuits while meeting the voltage requirements for both program and erase operations
2Reliability
If large erase voltage is applied to remove electrons from gate insulating layer, then erase operation is achieved, but power consumption increases significantly
Solution Approach 1:
The patent changes the voltage parameter by using a P-type semiconductor body that provides positive voltage during erase operations. This reduces the magnitude of voltage required compared to conventional negative voltage approaches, thereby reducing power consumption while maintaining effective electron removal from the gate insulating layer
3Reliability
If holes accumulate under the semiconductor layer for channel, then the Kink effect occurs, but conventional fabrication processes cannot prevent this
Solution Approach 1:
The patent extracts the harmful accumulated holes from the system by introducing a P-type semiconductor body that provides holes during erase operations. This prevents hole accumulation under the channel layer that causes the Kink effect, while the fabrication process remains simple by using standard semiconductor manufacturing techniques
4Reliability
If the number of masks and fabrication steps is increased to solve device problems, then device performance improves, but fabrication complexity and cost increase
Solution Approach 1:
The P-type semiconductor body serves multiple functions: it provides holes during erase operations to prevent the Kink effect, reduces the voltage magnitude required for erase operations, and eliminates the need for complex CMOS voltage generation circuits. This multi-functionality achieves device performance improvements without increasing fabrication complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integrated synaptic array structure reduces the number of masks and fabrication steps, lowers erase voltage requirements, suppresses the Kink effect, and enhances the efficiency of program and erase operations with reduced power consumption and improved memory window performance.
Implementation Method 1
the semiconductor body 230...is made of a semiconductor material doped with a second type of impurities opposite to the first type...providing holes to the semiconductor layer for channel during an erase operation
Implementation Method 2
oxide layers positioned between the semiconductor body and the source and between the semiconductor body and the drain
Data Source
AI summary
Provided is a synaptic array structure. The synaptic array structure includes: an isolation insulating layer positioned in a predetermined area on a semiconductor substrate to isolate devices; TFT-type synaptic devices arranged in an array on an isolation insulating layer; and CMOS peripheral circuits provided on the semiconductor substrate. The TFT-type synaptic device includes: a source and a drain positioned on the isolation insulating layer; a semiconductor body positioned between the source and the drain; oxide layers positioned between the semiconductor body and the source/drain; a semiconductor layer for channel; a TFT gate insulating layer; and a TFT gate electrode. The present invention, based on CMOS integration technology, processes TFT-type synaptic devices and CMOS peripheral circuits together, thereby reducing the number of masks and fabrication steps used during the fabricating process.