CMOS Quadrature Frequency Synthesizer for Fast Low-Power Hopping
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Solution Overview
Problem
Frequency synthesizers used in frequency hopping schemes face high power consumption and low signal-to-noise ratio due to high-frequency operations and the use of CML circuits, which also limit their ability to operate at low voltages.
Innovation Solution
The implementation of CMOS quadrature voltage-controlled oscillators and CMOS circuits reduces power consumption and increases the signal-to-noise ratio by eliminating the need for frequency dividers and using CMOS selectors and mixers, allowing for lower operating frequencies and reduced transistor cascading, thereby enabling operation at low voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If frequency dividers are used to generate four-phase signals from high-frequency VCO outputs, then frequency hopping capability is achieved, but power consumption increases due to high-frequency operation
Solution Approach 1:
The patent applies preliminary action by pre-generating four four-phase signals at lower frequencies using four separate VCOs, rather than generating a single high-frequency signal and then dividing it. This allows the frequency hopping to be achieved by selecting among pre-generated lower-frequency signals, thereby reducing power consumption while maintaining fast hopping capability.
Solution Approach 2:
The patent segments the single high-frequency VCO into four separate lower-frequency VCOs, each generating one of the four required phase signals. This segmentation allows each VCO to operate at a lower, more power-efficient frequency while collectively providing the same functional output as a single high-frequency VCO with frequency division.
2Speed
If CML circuits are used for high-speed operation, then frequency switching speed is improved, but signal-to-noise ratio decreases and low-voltage operation becomes difficult
Solution Approach 1:
The patent replaces the CML (Current Mode Logic) circuit system with a CMOS (Complementary Metal-Oxide-Semiconductor) circuit system. This substitution maintains the ability to achieve fast frequency switching while improving the signal-to-noise ratio and enabling low-voltage operation, as CMOS circuits operate with smaller current levels that reduce noise and allow for lower supply voltages.
3Speed
If CML circuits with cascaded MOS transistors are used, then high-frequency operation is achieved, but the number of transistors increases and low-voltage operation becomes impossible
Solution Approach 1:
The patent changes the operating parameters of the circuit by transitioning from CML to CMOS technology, which allows high-frequency operation with fewer cascaded transistors. The CMOS architecture inherently requires fewer transistor stages for the same frequency division function, thereby reducing device complexity and enabling operation at lower voltages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution results in a frequency synthesizer with reduced power consumption and improved signal-to-noise ratio, capable of fast frequency hopping and ultra-wide frequency range operation at low voltages.
Implementation Method 1
first and second voltage-controlled oscillators for generating four-phase signals
Implementation Method 2
a mixer for multiplying the four-phase signal selected by the selector by a four-phase input signal input from an external source to generate and output a signal having a frequency represented by the sum of, or the difference between, the frequency of the four-phase signal and the frequency of the four-phase input signal
Data Source
AI summary
A frequency synthesizer switches the frequency at a high rate, is of low power consumption, and has a high signal-to-noise ratio. CMOS quadrature VCOs 31, 32 generate and output four-phase signals 36, 37, respectively. CMOS selector 33 selects either one of two four-phase signals 36, 37 generated by CMOS quadrature VCOs 31, 32 and outputs the selected signal as output signal 38. CMOS SSB mixer 34 multiplies output signal 38 selected by CMOS selector 33 and four-phase input signal 39 input from an external source by each other to generate a signal having a frequency represented by the sum of, or the difference between, the frequency of output signal 38 and the frequency of four-phase input signal 39, and outputs the generated signal as output signal 40. CML buffer 35 adjusts the level of output signal 40 from CMOS SSB mixer 34 and outputs the level-adjusted signal to another circuit.