Tunable CMOS Template Matching for Low-Power Neural Spike Sorting
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Solution Overview
Problem
Current neural spike recording systems face challenges in achieving real-time spike sorting with low power dissipation and small area footprint, particularly in categorizing neural spikes in-vivo, while also requiring a hardware implementation of fuzzy logic for efficient data processing.
Innovation Solution
A tunable CMOS circuit with a memristor-based tunable load is used to determine exact matches between analogue input signals and pre-set switch points, enabling efficient spike sorting and fuzzy logic operations with minimal power dissipation and small area footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If fully digital or analogue techniques are used for spike detection, then detection accuracy is improved, but power dissipation and area footprint increase significantly
Solution Approach 1:
The patent replaces traditional operational amplifier-based analogue circuits with a CMOS inverter-based circuit that uses a tunable resistive load (memristor) to achieve spike detection. This substitution eliminates the need for expensive operational amplifies and analogue multiplier blocks, significantly reducing power dissipation and area footprint while maintaining detection functionality through the CMOS inverter's switching behavior controlled by the memristor's resistance state.
Solution Approach 2:
The patent dynamically changes the resistance parameter of the tunable load (memristor) to adjust the switch point voltage of the CMOS inverter. By programming the memristor's resistance, the circuit can be tuned to detect specific spike amplitudes and shapes, enabling accurate spike detection and sorting without requiring complex analogue signal conditioning circuits, thus achieving low power consumption with high detection precision.
2Adaptability or versatility
If operational amplifies and analogue multiplier blocks are used, then signal processing capability is improved, but area footprint and power consumption increase
Solution Approach 1:
The patent creates a universal spike detection and sorting circuit using a single CMOS inverter with a programmable memristor load. This unified circuit structure can perform multiple functions including spike detection, amplitude thresholding, and waveform sorting by simply reprogramming the memristor's resistance, eliminating the need for separate operational amplifies, analogue multipliers, and other dedicated signal processing blocks, thereby achieving high adaptability with minimal area footprint.
Solution Approach 2:
The patent extracts the essential spike detection functionality from complex analogue signal processing chains and implements it using a minimal CMOS inverter circuit with a tunable resistive load. By removing unnecessary operational amplifies and analogue multiplier blocks, the design achieves the core signal processing capability with dramatically reduced area and power while maintaining the ability to detect and categorize neural spikes.
3Measurement precision
If complex spike sorting algorithms are implemented, then categorization accuracy is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent replaces complex digital signal processing algorithms with an analogue-inspired CMOS inverter circuit whose switching behavior naturally performs spike categorization. The memristor's resistance state is programmed to represent different spike templates, and the inverter's response to input signals automatically categorizes spikes based on their similarity to these templates, achieving high categorization accuracy without complex digital logic or algorithms.
Solution Approach 2:
The patent enables the CMOS inverter circuit to autonomously perform spike detection and categorization without requiring external control logic or complex processing algorithms. The memristor-programmed switch point voltage automatically adapts the circuit's detection threshold and characteristics, allowing the circuit to self-adjust and self-categorize spikes based on their amplitude and temporal features, significantly reducing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for real-time in-vivo spike sorting and categorization with low power consumption and small area requirements, while providing a flexible hardware implementation of fuzzy logic, effectively extracting useful information from high-bandwidth neural signals.
Implementation Method 1
In an embodiment, the tunable load comprises one or more memristors. A memristor may store the switch point value in an area-efficient manner, due to its back-end-of-line integrability.
Implementation Method 2
In an embodiment, a first CMOS stage and/or a second CMOS stage of the CMOS element comprises a CMOS inverter. The CMOS inverter is the smallest CMOS building block.
Data Source
AI summary
A tunable CMOS circuit comprising a CMOS element and a tunable load. The CMOS element is configured to receive in an analogue input signal. The tunable load is connected to the CMOS element and configured to set a switch point of the CMOS element. The CMOS element is configured to output an output current that is largest when the analogue input signal is equal to the switch point. The combination of a CMOS element with a tunable load may also provide a hardware implementation of fuzzy logic. A fuzzy logic gate comprises an input node, a CMOS logic gate including a tunable load, and an output node. The input node is configured to receive an analogue input signal. The CMOS logic gate is connected to the input node. The tunable load is provided on a current path connected to the output node. The output node is configured to output an analogue output signal.