CMOS-TFT Semiconductor Structure With Leveled Capping Layers
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Solution Overview
Problem
Integrating high-power, high-frequency, and high-speed thin-film transistors (TFT) devices into traditional CMOS logic processes is challenging due to complexity and cost, with a need to simplify the overall process and reduce manufacturing costs while controlling thermal budgets.
Innovation Solution
The integration of high-voltage TFT devices into the front-end-of-line (FEOL) of CMOS logic processes, where active areas for TFT devices are defined before CMOS logic device formation, using a substrate with a TFT channel layer, MOSFET, and interlayer dielectric layers functioning as a gate dielectric, and forming TFT and MOSFET components in a sequential manner to reduce process steps and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If TFT devices are integrated into traditional CMOS logic process, then device performance and functionality are improved, but process complexity and manufacturing cost increase
Solution Approach 1:
The patent merges TFT and CMOS process flows into a unified integrated process. The TFT active area definition, channel layer formation, and gate electrode creation are combined with CMOS well formation and transistor fabrication steps, allowing both device types to be manufactured simultaneously on the same substrate through a single integrated process sequence.
Solution Approach 2:
The patent creates a universal process platform that can manufacture both TFT devices and CMOS logic devices using the same sequence of process steps. The integrated FEOL process serves multiple functions: defining TFT active areas, forming TFT channel layers, creating CMOS wells, and fabricating CMOS transistors, all within a single multi-functional manufacturing flow.
2Adaptability or versatility
If TFT devices are integrated into CMOS process, then overall functionality is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines TFT and CMOS manufacturing into a single integrated process, eliminating the need for separate production lines. By merging the process flows, the patent achieves economies of scale, reduces equipment and facility requirements, and lowers overall manufacturing costs while maintaining the ability to produce both device types with high functionality.
3Device complexity
If TFT active areas are defined after CMOS well formation, then process sequencing is simplified, but thermal budget control deteriorates
Solution Approach 1:
The patent performs preliminary action by defining TFT active areas and forming TFT channel layers before CMOS well formation and transistor fabrication. This sequencing allows the TFT structures to be established early in the process when thermal conditions are more controlled, enabling better thermal budget management while maintaining straightforward process sequencing through careful step-by-step execution.
Data Source
AI summary
The present invention provides a semiconductor structure, including a substrate, a thin-film transistor (TFT) on the substrate, wherein the thin-film transistor including a TFT channel layer, a first source and a first drain in the TFT channel layer and a first capping layer on the TFT channel layer. A MOSFET is on the substrate, with a second gate, a second source and a second drain on two sides of the second gate and a second capping layer on the second gate, wherein top surfaces of the second capping layer and the first capping layer are leveled, and a first ILD layer is on the first capping layer and the second capping layer, wherein the first ILD layer and the first capping layer function collectively as a gate dielectric layer for the TFT.