CMOS Thermoelectric Device Isolation Trenches
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Solution Overview
Problem
Integrated circuits with CMOS transistors and thermoelectric devices face challenges due to high electrical resistance in thermoelectric elements and substrate regions, which hinders their performance.
Innovation Solution
The formation of isolation trenches in a substrate to define active areas for both CMOS transistors and thermoelectric elements, with dielectric material providing field oxide for lateral isolation, and the use of n-type and p-type dopants implanted at high densities to reduce electrical resistance between thermoelectric elements and the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If thermoelectric elements are integrated into CMOS circuits, then device functionality is improved, but electrical resistance increases
Solution Approach 1:
The patent applies local quality by creating heavily doped n-type and p-type regions specifically at the contact points between thermoelectric elements and the substrate. This localized doping provides low electrical resistance paths only where needed for current flow, while maintaining the isolation benefits of the substrate in other areas. The selective doping regions are formed using implant masks that target specific geometric areas, allowing different electrical properties in different locations of the same substrate.
Solution Approach 2:
The patent implements preliminary action by forming the heavily doped contact regions and isolation structures before completing the thermoelectric element fabrication. The isolation trenches are etched and filled with dielectric material, and the dopant regions are implanted into the substrate in advance, creating a prepared substrate structure that minimizes resistance pathways before the thermoelectric elements are fully assembled.
2Reliability
If isolation trenches are formed to separate CMOS and thermoelectric areas, then lateral isolation is improved, but manufacturing complexity increases
Solution Approach 1:
The isolation trenches serve multiple functions simultaneously: they provide lateral electrical isolation between CMOS and thermoelectric areas, define the geometric boundaries of active regions, and serve as etch stop layers during subsequent processing. The dielectric material filling the trenches also provides mechanical support and stress management. This multi-functionality reduces the need for separate isolation structures and simplifies the overall manufacturing process.
Solution Approach 2:
The patent merges the isolation function with the region definition function by using the same isolation trenches to both electrically separate areas and define the active areas for thermoelectric elements and CMOS devices. The implant masks are also designed to align with these trench boundaries, combining multiple patterning functions into a single geometric framework that reduces the number of separate fabrication steps required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces electrical resistance, improving the performance of the embedded thermoelectric device by enhancing the integration of low-resistance thermoelectric elements within the integrated circuit.
Implementation Method 1
N-type dopants are implanted into the substrate exposed by the n-type implant mask to provide at least 1×10^18 cm^-3 n-type dopants in the areas for n-type thermoelectric elements and the substrate under the isolation trenches between the areas for the n-type thermoelectric elements
Implementation Method 2
P-type dopants are implanted into the substrate exposed by the p-type implant mask to provide at least 1×10^18 cm^-3 p-type dopants in the areas for p-type thermoelectric elements and the substrate under the isolation trenches between the areas for the p-type thermoelectric elements
Implementation Method 3
Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements
Data Source
AI summary
An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the CMOS transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1×1018 cm−3 n-type dopants in n-type thermoelectric elements and the substrate under the field oxide between the n-type thermoelectric elements. P-type dopants are implanted into the substrate to provide at least 1×1018 cm−3 p-type dopants in p-type thermoelectric elements and the substrate under the field oxide between the p-type thermoelectric elements. The n-type dopants and p-type dopants may be implanted before the field oxide are formed, after the isolation trenches for the field oxide are formed and before dielectric material is formed in the isolation trenches, and/or after the field oxide is formed.