Stacked CMOS Image Sensor Through-Hole Layout for Reliable Chip Interconnects

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Solution Overview

Problem

Existing image sensors face connection failure issues due to inadequate interconnection structures, which can lead to reduced integration density and performance in high-demand applications.

Innovation Solution

The image sensor design incorporates a through-hole structure with trenches and interconnection patterns on both sides, allowing for a more robust connection between the sensor chip and logic chip, utilizing conductive layers and insulating layers to ensure electrical connectivity while minimizing light interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a simple through-hole structure is used for connecting sensor chip and logic chip, then the manufacturing process is simple, but connection failure occurs due to inadequate interconnection

Engineering Contradiction:
Improveconnection reliabilityVSAvoidinterconnection structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The through-hole is segmented into multiple trenches (first trench, second trench, third trench) that extend to different depths and contact different interconnection patterns. This segmentation allows each trench to serve a specific connection function, improving connection reliability while maintaining manufacturing feasibility through standardized patterning processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The interconnection structure transitions from a simple planar connection to a three-dimensional multi-level trench system. The trenches extend vertically through the substrate at different positions, creating depth variation that enables multiple connection paths and improves reliability without significantly increasing lateral footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If a robust interconnection structure with multiple trenches is implemented, then connection reliability improves, but manufacturing complexity increases

Engineering Contradiction:
Improveconnection reliabilityVSAvoidmanufacturing ease
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The first interconnection pattern is formed in the substrate before the trenches are etched. This preliminary patterning allows the trenches to be precisely positioned and sized to match the existing interconnection patterns, ensuring reliable electrical contact while using standard semiconductor fabrication sequences that maintain manufacturing ease.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The trenches are nested within the overall through-hole structure, with each trench positioned strategically to contact specific interconnection patterns. The smaller trenches are contained within the larger through-hole footprint, allowing multi-functional interconnection within a compact geometry that simplifies alignment and manufacturing.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Reliability

If the bottom surface of through-hole is positioned lower to contact first interconnection pattern, then electrical connectivity is ensured, but light interference increases

Engineering Contradiction:
Improveelectrical connectivityVSAvoidlight interference
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The trenches are positioned locally at specific positions within the through-hole rather than uniformly distributed. The first, second, and third trenches are strategically located to contact specific interconnection patterns while minimizing their overall footprint. This localized positioning ensures electrical connectivity at critical points while reducing the total area that could interfere with light propagation to the photodiode.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12068350B2Complementary metal-oxide semiconductor (CMOS) image sensor
Publication Date: 2024.08.20 SAMSUNG ELECTRONICS CO LTD
  • US12068350B2 patent drawing
  • US12068350B2 patent drawing
  • US12068350B2 patent drawing

AI summary

Provided is an image sensor including a sensor chip including a first substrate and a first interconnection layer, a logic chip including a second substrate and a second interconnection layer, a through-hole penetrating a portion of the second interconnection layer, the first substrate, and the first interconnection layer, and a first connection structure disposed on an inner surface of the through-hole and extending from the first substrate toward the second interconnection layer, wherein the first interconnection layer includes a first interlayer insulating layer and a first interconnection pattern, the second interconnection layer includes a second interlayer insulating layer and a second interconnection pattern, the through-hole includes first and second trenches respectively extending from the through-hole toward the second interconnection layer, bottom surfaces of the first and second trenches contact the second interconnection pattern, and a bottom surface of the through-hole contacts the first interconnection pattern.