CMOS Tile Interconnects for Large-Area X-Ray Detector Resolution
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Solution Overview
Problem
Current X-ray detector technologies face challenges in achieving high resolution and low electronic noise due to limitations in amorphous silicon (a-Si) technology, while crystalline silicon (c-Si) technology offers better performance but is costly and limited by silicon wafer size, requiring complex tiling arrangements that are difficult to implement effectively.
Innovation Solution
The use of four-side buttable CMOS tiles with through-silicon-vias, tile-to-tile interconnects, transparent sheet interconnects, and 3D printed interconnects allows for the assembly of large-area detector panels by enabling electrical connections and readout at multiple levels, facilitating the integration of readout electronics within each tile for efficient data acquisition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If amorphous silicon (a-Si) technology is used for large-area X-ray detectors, then large area capability and competitive cost are achieved, but electron mobility is much lower resulting in higher electronic noise and lower resolution
Solution Approach 1:
The detector panel is divided into multiple smaller CMOS tiles that can be individually fabricated on standard-sized silicon wafers and then assembled into a large-area detector array. This segmentation allows each tile to benefit from high electron mobility of crystalline silicon while the overall system achieves large detector area through tiling.
2Measurement precision
If crystalline silicon (c-Si) CMOS technology is used to improve resolution and reduce electronic noise, then electron mobility increases, but panel size is limited by silicon wafer size requiring complex tiling arrangements
Solution Approach 1:
A specialized interconnect structure with conductive traces and vias serves as an intermediary between adjacent CMOS tiles, enabling electrical connections to be made at the boundaries between tiles. This intermediary structure simplifies the tiling arrangement by providing standardized connection points that facilitate modular assembly without complex wiring.
3Area of stationary object
If multiple smaller panels are tiled together to achieve useful detector panel size, then large area capability is achieved, but electrical interconnection arrangements become complex and difficult to implement
Solution Approach 1:
Conductive traces and vias are pre-formed on each CMOS tile during the fabrication process, establishing electrical connection pathways before the tiles are assembled. This preliminary action simplifies the assembly process by eliminating the need for complex post-assembly wiring, as the electrical interconnections are already prepared on each tile.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of large-area X-ray panels with improved resolution and reduced electronic noise, while simplifying the assembly process and potentially lowering costs by using smaller, more precise CMOS tiles that can be arranged to form panels of any size, maintaining image quality and stability.
Implementation Method 1
The scintillator of the detector converts the higher-energy X-ray radiation to lower-energy light photons that are sensed using photo-sensitive components
Implementation Method 2
light photons that are sensed using photo-sensitive components (e.g., photodiodes or other suitable photodetectors)
Data Source
AI summary
Various approaches are discussed for using four-side buttable CMOS tiles to fabricate detector panels, including large-area detector panels. Fabrication may utilize pads and interconnect structures formed on the top or bottom of the CMOS tiles. Electrical connection and readout may utilize readout and digitization circuitry provided on the CMOS tiles themselves such that readout of groups or sub-arrays of pixels occurs at the tile level, while tiles are then readout at the detector level such that readout operations are tiered or multi-level.