CMOS Tile Radiation Detector Assembly via Segmentation
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Solution Overview
Problem
Current X-ray detector technologies face challenges in achieving high resolution and low electronic noise due to limitations in amorphous silicon (a-Si) technology, while crystalline silicon (c-Si) technology offers better performance but is hindered by higher costs and smaller panel sizes due to wafer size limitations, making it impractical for large-area detectors.
Innovation Solution
The use of four-side buttable CMOS tiles with various interconnection methods, such as through-silicon-vias, tile-to-tile interconnects, and optically transparent layers, allows for the assembly of large-area detector panels with improved yield and reduced costs, enabling higher resolution and lower noise performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If amorphous silicon (a-Si) technology is used for large-area X-ray detectors, then large panel size and low cost are achieved, but resolution and electronic noise performance deteriorate
Solution Approach 1:
The detector panel is divided into multiple smaller CMOS tiles that can be tiled together to form a large-area detector. Each tile is fabricated using c-Si technology on standard-size wafers, and the tiles are arranged in a grid pattern with interconnection structures (such as conductive bridges or transparent conductive oxides) enabling electrical connections between adjacent tiles. This segmentation allows the system to achieve both high resolution (from c-Si) and large area (from tiling) simultaneously.
2Measurement precision
If crystalline silicon (c-Si) technology is used for high resolution detectors, then resolution and electronic noise performance are improved, but panel size is limited by wafer size
Solution Approach 1:
The detector panel is divided into multiple smaller CMOS tiles that can be tiled together to form a large-area detector. Each tile is fabricated using c-Si technology on standard-size wafers, and the tiles are arranged in a grid pattern with interconnection structures (such as conductive bridges or transparent conductive oxides) enabling electrical connections between adjacent tiles. This segmentation allows the system to achieve both high resolution (from c-Si) and large area (from tiling) simultaneously.
3Area of stationary object
If multiple CMOS tiles are tiled together to form large-area detectors, then large panel size is achieved, but electrical interconnection complexity increases
Solution Approach 1:
Adjacent CMOS tiles are connected through shared interconnection structures that span the boundaries between tiles. Conductive bridges are formed along the side walls of adjacent tiles, or transparent conductive oxide layers are deposited across tile boundaries, allowing electrical connections to be made between neighboring tiles. This merging approach reduces the number of separate interconnection paths needed and simplifies the overall wiring architecture.
Solution Approach 2:
Transparent conductive oxide (TCO) layers are used as intermediary conductive elements that span across tile boundaries to establish electrical connections between adjacent CMOS tiles. The TCO layer acts as a mediator that provides continuous electrical pathways across the gaps between tiles without requiring complex wire bonds or solder connections, thereby reducing interconnection complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of large-area X-ray panels with higher resolution and lower electronic noise, overcoming the limitations of a-Si technology while reducing costs and simplifying the assembly of complex electrical interconnections.
Implementation Method 1
The scintillator of the detector converts the higher-energy X-ray radiation to lower-energy light photons that are sensed using photo-sensitive components
Implementation Method 2
light photons that are sensed using photo-sensitive components (e.g., photodiodes or other suitable photodetectors)
Data Source
AI summary
Various approaches are discussed for using four-side buttable CMOS tiles to fabricate detector panels, including large-area detector panels. Fabrication may utilize pads and interconnect structures formed on the top or bottom of the CMOS tiles. Electrical connection and readout may utilize readout and digitization circuitry provided on the CMOS tiles themselves such that readout of groups or sub-arrays of pixels occurs at the tile level, while tiles are then readout at the detector level such that readout operations are tiered or multi-level.