CMOS Transmission Circuit Layout for Single-Event Transient Blocking
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Solution Overview
Problem
Conventional CMOS circuits formed on silicon substrates lack effective countermeasures against single event transients and upsets due to high-energy charged particles, especially with advancements in microfabrication making it difficult to maintain necessary spatial distances between components.
Innovation Solution
A CMOS circuit design incorporating a first logical operation circuit with specific transistor configurations and a transmission circuit connected to its output terminal, utilizing transistors of different conductivity types and well connections to prevent single event transients from propagating by turning off the transmission gate circuit upon particle incidence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If circuit elements are formed on a bulk substrate without SOI structure, then manufacturing cost is reduced, but resistance to single event effects deteriorates
Solution Approach 1:
The circuit element is segmented into two identical or different circuit blocks arranged in series. Each block includes transistors with sources connected to drains of other transistors, creating distinct functional segments that can independently handle single event effects.
Solution Approach 2:
The patent applies different conductivity types to different regions of the circuit. P-type and N-type transistors are strategically placed in specific locations within the circuit blocks, with their wells and substrates having complementary conductivity types to create local electrical characteristics that resist single event effects.
2Reliability
If spatial distance between circuit components is increased to prevent single event propagation, then resistance to single event effects is improved, but circuit element size increases
Solution Approach 1:
One circuit block is nested within or adjacent to another circuit block with complementary transistor arrangements. The P-type and N-type transistor blocks are interlaced or positioned such that they share space efficiently while maintaining the series connection topology, reducing the overall area compared to widely spaced components.
Solution Approach 2:
The circuit elements are arranged in a vertical or multi-layer configuration rather than purely horizontal spacing. Transistors are stacked or positioned in different planes, allowing single event effect prevention through spatial separation in multiple dimensions while minimizing the footprint area.
3Manufacturing precision
If conventional single event countermeasures are applied to microfabricated circuits, then manufacturing precision is improved, but effectiveness of single event countermeasures deteriorates
Solution Approach 1:
The patent changes the electrical parameters of the circuit by using complementary conductivity types (P-type and N-type) in series configuration. This parameter change creates opposite polarity regions that naturally counteract single event effects through electrical field cancellation rather than relying on physical distance, making it effective for microfabricated circuits.
Solution Approach 2:
The circuit employs a composite structure combining P-type and N-type transistors in a series configuration. This composite arrangement integrates two different conductivity type materials/structures to create a system that leverages the complementary electrical characteristics of both types to resist single event effects.
Data Source
AI summary
In a complementary metal oxide semiconductor (CMOS) circuit formed on a substrate of a first conductivity type, a first logical operation circuit includes a combination of a first transistor of the first conductivity type having a first well of a second conductivity type different from the first conductivity type and a second transistor of the second conductivity type having a second well of the first conductivity type and a transmission circuit is connected to an output terminal of the first logical operation circuit and includes one or both of a third transistor of the first conductivity type and a fourth transistor of the second conductivity type. Each of gate terminals of the third transistor and the fourth transistor is connected to a well of a transistor of a different conductivity type between the first transistor and the second transistor or an output terminal of a second logical operation circuit.