CMOS Transistor Fabrication Using Mask Layer Isolation
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Solution Overview
Problem
In the manufacturing of CMOS transistors, there is a challenge in preventing mutual influence between n-type and p-type semiconductor layers, which affects the reliability and electrical characteristics of the device.
Innovation Solution
A fabricating method is developed where a mask layer is used to isolate the n-type and p-type channel layers, preventing direct contact and subsequent etching damage, and a passivation layer is applied to ensure electrical connectivity while protecting the layers from mutual interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the p-type channel layer and n-type channel layer are formed in contact with each other to accomplish system-on-glass circuits, then productivity is improved by forming both transistor types simultaneously, but the channel layers affect each other causing changes in inherent semiconductor characteristics and reliability deteriorates
Solution Approach 1:
The patent divides the channel layer formation process into separate sequential steps for p-type and n-type transistors, with the first channel layer formed, processed, and protected before forming the second channel layer. This segmentation prevents mutual influence between the two semiconductor layers while maintaining productivity through integrated processing steps.
Solution Approach 2:
The patent introduces an intermediary protective layer (such as a mask layer or passivation layer) between the p-type and n-type channel layers during processing. This intermediary prevents direct contact and mutual contamination between the two channel layers, preserving their inherent semiconductor characteristics while allowing both to be formed on the same substrate.
2Device complexity
If the p-type and n-type oxide TFTs are etched using the same process, then manufacturing complexity is reduced, but the etchant may damage the opposite type transistor and manufacturing precision deteriorates
Solution Approach 1:
The patent applies preliminary protective actions by forming a protective layer over the first channel layer before etching the second channel layer. This preliminary protection ensures that when the same etchant is used for both transistor types, only the intended layer is affected, preventing damage to the opposite type transistor and maintaining high manufacturing precision.
Solution Approach 2:
The protective layer serves as an intermediary that allows the use of a universal etching process for both p-type and n-type transistors while preventing the etchant from damaging the opposite type. This intermediary enables manufacturing simplicity through unified etching steps while preserving manufacturing precision by protecting vulnerable structures.
Data Source
AI summary
A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.