CMOS Transistor Pair with Different Gate Oxide Thicknesses for Unclonable Chip ID
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Solution Overview
Problem
Existing hardware identification systems for integrated circuit chips, such as e-fuses and PUFs, face challenges in increasing manufacturing costs, decoding vulnerabilities, and reduced variability with technological maturity, necessitating a more secure and stable unique identification method.
Innovation Solution
The use of transistor pairs with different gate oxide thicknesses, programmed using bias temperature instability (BTI), to produce unique and stable threshold voltage distributions, enabling a secure and unclonable chip ID through a balanced latch and cross-coupled inverters, which generates a unique bit string for identification purposes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If e-fuses are used for chip identification, then chip ID functionality is achieved, but manufacturing costs increase due to additional testing time
Solution Approach 1:
The patent uses naturally occurring, disposable physical variations in transistor threshold voltages that exist without any additional manufacturing steps. Each transistor's unique threshold voltage, determined by inherent physical variations during standard fabrication, serves as a one-time programmable identifier that requires no extra testing or programming time.
Solution Approach 2:
The transistors self-program their own unique identifiers through inherent physical variations in threshold voltage that occur naturally during the manufacturing process. No external programming, testing, or additional processing is required - the identifiers are automatically generated by the physical properties of the transistors themselves.
2Reliability
If e-fuses are used for chip identification, then chip ID functionality is achieved, but security is reduced due to vulnerability to decoding and copying
Solution Approach 1:
The patent exploits local physical variations in each individual transistor's threshold voltage, which are determined by unique local defects and material properties at the microscopic level. These local variations create identifiers that are inherently unique to each device and cannot be replicated by examining or copying the overall device structure.
Solution Approach 2:
The patent converts the traditionally harmful effect of manufacturing variations and defects into a beneficial security feature. The random threshold voltage offsets caused by physical variations, which were previously considered noise or errors, are now exploited as the basis for unclonable device identifiers that provide inherent security against copying.
3Reliability
If memory-based PUFs are used for chip identification, then unique identifiers are generated, but reliability decreases as memory cells become more stable with technology maturation
Solution Approach 1:
The patent replaces memory-based PUF mechanisms with a direct electrical measurement approach. Instead of using memory cell states or retention properties, the system directly measures the threshold voltage of transistors, which are determined by fundamental physical properties of the semiconductor material and device structure that do not degrade with technology scaling.
Solution Approach 2:
The patent changes the fundamental parameter being measured from memory cell retention characteristics to transistor threshold voltage. Threshold voltage is determined by physical properties such as oxide thickness and doping profiles that remain sufficiently variable even as technology scales, providing stable and reliable identifiers across different technology nodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides a secure, stable, and unclonable chip ID that is resistant to cloning and physical inspection, leveraging BTI-induced variability to create unique identifiers on each chip, reducing manufacturing costs and enhancing security without relying solely on manufacturing-induced variability.
Implementation Method 1
programmed using bias temperature instability (BTI) to produce unique and stable threshold voltage distributions
Data Source
AI summary
Methods and devices for providing unclonable chip identification are provided. An integrated circuit device includes: a first transistor having a first gate oxide thickness; a second transistor having a second gate oxide thickness different than the first gate oxide thickness; and a reading circuit connected to the first transistor and the second transistor, wherein the reading circuit reads a difference in threshold voltage between the first transistor and the second transistor.