CMOS Transistor Stress Engineering for Leakage Control
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Solution Overview
Problem
The challenge in manufacturing semiconductor CMOS transistors is the limitation in further shrinking due to current leakage issues, particularly with gate oxides, which restricts performance improvements.
Innovation Solution
The implementation of crystal strain technology by using tensile-stressed silicon nitride layers on NMOS transistors and compressive-stressed silicon nitride layers on PMOS transistors to enhance charge mobility, with the layers being deposited using plasma-enhanced chemical vapor deposition (PECVD) to achieve stress levels greater than 1 Gpa, thereby optimizing transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate oxide is thinned to increase transistor speed, then transistor speed is improved, but current leakage increases
Solution Approach 1:
The patent changes the physical state and properties of the silicon nitride layer by controlling deposition parameters (PECVD conditions, temperature, pressure) to achieve different stress levels. By adjusting these parameters, the silicon nitride layer can be made tensile-stressed for NMOS or compressive-stressed for PMOS, thereby modifying charge mobility without changing gate oxide thickness
Solution Approach 2:
The patent applies different stress conditions to different transistor types: tensile stress is applied specifically to NMOS devices while compressive stress is applied to PMOS devices. This local differentiation optimizes each transistor type's performance characteristics independently, enhancing electron mobility in NMOS and hole mobility in PMOS without affecting the other
2Area of moving object
If transistor size is reduced to increase density, then device density is improved, but manufacturing precision becomes more difficult
Solution Approach 1:
The silicon nitride stress layer acts as an intermediary element that is deposited over the existing transistor structure. This intermediary layer provides the stress effect needed for mobility enhancement without requiring direct modification of the gate oxide or channel dimensions, thereby avoiding additional precision requirements at the smallest feature sizes
Solution Approach 2:
The patent segments the stress application process into distinct stages: first forming the basic transistor structure, then depositing the silicon nitride layer with specific stress characteristics. This segmentation allows each process step to be optimized independently, with the stress layer deposition being a separate, controllable step that does not complicate the miniaturization of other transistor components
3Speed
If crystal strain technology is applied to enhance charge mobility, then charge mobility is improved, but device complexity increases
Solution Approach 1:
The silicon nitride layer serves multiple functions: it provides stress-induced mobility enhancement, acts as a deposition platform using existing PECVD infrastructure, and can be selectively applied to different transistor types. This multi-functionality achieves mobility improvement without requiring entirely new manufacturing equipment or processes
Solution Approach 2:
The patent converts the naturally occurring compressive stress in silicon nitride (which would normally be considered a fixed property) into a beneficial feature for PMOS devices, while using process control to create tensile stress for NMOS devices. What could be seen as a limitation (fixed stress type) becomes a controllable parameter that benefits different device types
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the mobility of electrical charges in CMOS transistors, specifically increasing electron mobility in N-type transistors while maintaining performance for P-type transistors, thus enhancing overall transistor speed and efficiency.
Implementation Method 1
the layers being deposited using plasma-enhanced chemical vapor deposition (PECVD) to achieve stress levels greater than 1 Gpa
Implementation Method 2
The implementation of crystal strain technology by using tensile-stressed silicon nitride layers on NMOS transistors to enhance charge mobility
Implementation Method 3
compressive-stressed silicon nitride layers on PMOS transistors to enhance charge mobility
Data Source
AI summary
A CMOS transistor device including a tensile-stressed NMOS transistor and a PMOS transistor is disclosed. The NMOS transistor includes a gate, a gate oxide layer between the gate and semiconductor substrate, a silicon oxide offset spacer on sidewalls of the gate, N type lightly doped source/drain implanted into the semiconductor substrate next to the silicon oxide offset spacer, N type heavily doped source/drain implanted into the semiconductor substrate next to the N type lightly doped source/drain, and tensile-stressed silicon nitride layer covering the gate, the N type lightly doped source/drain, and the N type heavily doped source/drain.