Parallel CMOS Data Transitions for Power-Supply Jitter Filtering
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
CMOS circuitry in integrated circuits introduces jitter into data signals due to propagation delays and power supply noise, which affects signal quality, especially in communication systems where precise timing is crucial.
Innovation Solution
The implementation of additional CMOS circuitry connected to the same power supply as the primary circuitry, with a second data signal generated by inverting every second bit of the original signal, ensures a data transition occurs in either circuitry every bit period, effectively filtering noise and reducing jitter by making the data frequency content more narrowband and easier to filter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If CMOS circuitry is used in the data path to prepare data signals, then lower cost and higher speed are achieved, but jitter is introduced into the data signal
Solution Approach 1:
The patent utilizes the power supply noise that causes jitter and converts it into a beneficial filtering mechanism. By intentionally modulating the power supply with data transitions, the noise energy is concentrated at the data rate frequency, which can then be filtered out more effectively, converting the harmful jitter into a controllable and removable disturbance.
Solution Approach 2:
The patent changes the frequency domain characteristics of the power supply noise by modifying when data transitions occur. By controlling the timing of data transitions to align with the data rate, the noise spectrum is shaped to concentrate energy at specific frequencies that are easier to filter, thereby changing the parameter of noise frequency distribution.
2Reliability
If additional CMOS circuitry is added to create data transitions every bit period, then jitter is reduced by filtering power supply noise, but device complexity increases
Solution Approach 1:
The additional CMOS circuitry serves multiple functions: it generates data transitions for noise modulation, acts as a parallel processing path, and contributes to the overall data signal preparation. This multi-functionality justifies the added complexity by providing several benefits from a single circuit addition.
Solution Approach 2:
The patent creates a copy of the data signal path with inverted every-other-bit patterns. This copied circuitry mirrors the functionality of the original path but with modified timing characteristics, allowing the system to achieve noise filtering without completely redesigning the signal processing architecture.
3Reliability
If data transitions are forced to occur every bit period, then power supply noise is concentrated at data rate frequency for better filtering, but the natural data signal characteristics are altered
Solution Approach 1:
The patent segments the data signal processing into two parallel paths: one handling the original data signal and another handling the inverted every-other-bit signal. This segmentation allows each path to be optimized for its specific function while maintaining the overall data integrity through combination of both paths.
Solution Approach 2:
The power supply acts as an intermediary medium that carries the modulated noise signal. By using the power supply as the transmission medium for noise modulation, the patent avoids directly altering the data signal path while still achieving noise concentration at the data rate frequency.
Data Source
AI summary
When a data path includes CMOS circuitry, such circuitry may introduce jitter into the data signal. Embodiments are described in which additional data transitions are made to occur, and these additional data transitions may change the characteristics of the data frequency content transferred to the power supply so that such noise may be better filtered. This may have an effect of reducing jitter in the data signal. In one embodiment, a second data signal is generated to be a version of a first data signal with every second bit inverted. Second CMOS circuitry receives the second data signal in parallel to first CMOS circuitry receiving the first data signal. The first CMOS circuitry and the second CMOS circuitry are connected to a same power supply.