CMOS Image Sensor Trench Capacitor Area Reduction
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Solution Overview
Problem
Conventional CMOS image sensors face challenges in miniaturization due to the large area occupied by planar-structured capacitors in peripheral circuitry, which limits scalability and hinders the achievement of faster processing speeds and better image quality.
Innovation Solution
The implementation of trench capacitors in peripheral circuitry reduces the physical area required for large-value capacitors, providing increased capacitance while maintaining or reducing the semiconductor die size, achieved through a trench structure with a dielectric layer, polysilicon layer, and a doped epi layer as electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar-structured capacitors are used in peripheral circuitry, then sufficient capacitance can be achieved, but the semiconductor die area increases significantly
Solution Approach 1:
The patent transitions from planar-structured capacitors to trench capacitors, moving the capacitor structure into the third dimension by etching trenches into the semiconductor substrate. This vertical configuration allows the capacitor electrodes to extend downward into the substrate, significantly increasing the effective capacitance area without occupying additional planar surface area on the semiconductor die.
2Quantity of substance
If planar-structured capacitors are used in peripheral circuitry, then sufficient capacitance can be achieved, but the semiconductor die size increases by approximately 15%
Solution Approach 1:
The trench capacitor structure utilizes the vertical dimension by etching deep trenches into the semiconductor substrate. The capacitor electrodes are formed within these trenches, extending vertically rather than horizontally. This dimensional transition provides the required capacitance while minimizing the horizontal footprint, thereby preventing the 15% increase in semiconductor die size that would result from using planar-structured capacitors.
3Quantity of substance
If larger semiconductor die size is used to accommodate planar capacitors, then sufficient capacitance is available, but miniaturization and scalability are limited
Solution Approach 1:
By implementing trench capacitors that extend vertically into the semiconductor substrate, the patent enables sufficient capacitance to be achieved within a compact planar footprint. This vertical configuration supports continued miniaturization and scaling of the semiconductor die, as the capacitor structures do not consume additional horizontal space that would otherwise be available for pixel arrays or other functional elements.
Solution Approach 2:
The trench capacitor structure nests the capacitor electrodes within the semiconductor substrate itself, utilizing the substrate volume that would otherwise be empty space. The trenches are etched into the existing substrate, and the capacitor electrodes are formed within these recesses, effectively nesting the capacitor structure within the semiconductor device architecture without requiring additional external space.
Data Source
AI summary
An example complementary metal oxide semiconductor (CMOS) image sensor includes an epitaxial layer, an array of pixels, and a trench capacitor. The array of pixels are formed on a front side of the epitaxial layer in an pixel array area of the image sensor. The array of pixels includes one or more shallow trench isolation structures disposed between adjacent pixels for isolating the pixels in the pixel array area. The trench capacitor is formed on the front side of the epitaxial layer in a peripheral circuitry area of the image sensor.