CMOS Voltage Reference Circuit for Zero-Temperature Stability
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Solution Overview
Problem
Conventional voltage reference circuits using bipolar junction transistors (BJTs) and CMOS devices are susceptible to substrate noise, failing to provide a fully temperature-independent reference voltage due to sensitivity to majority and minority carrier noise.
Innovation Solution
A voltage reference circuit employing a flipped-gate transistor with an anti-doped gate electrode and a non-flipped-gate transistor, where the current ratio between the flipped-gate and non-flipped-gate transistors is adjusted to achieve a zero-temperature coefficient (ZTC) operating point, ensuring the reference voltage remains temperature-insensitive across various temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bipolar junction transistors (BJTs) are used to form bandgap references, then a reference voltage can be provided, but the circuit becomes sensitive to substrate noise (majority carrier noise in PNP BJTs and minority carrier noise in NPN BJTs)
Solution Approach 1:
The patent extracts the problematic BJT components from the voltage reference circuit and replaces them entirely with CMOS devices. This removal eliminates the substrate noise sensitivity inherent in BJTs while maintaining the voltage reference functionality through alternative CMOS-based mechanisms such as folded-cascode amplifiers and current mirrors.
Solution Approach 2:
The patent introduces triple-well isolation structures as intermediary elements between the CMOS devices and the substrate. This isolation layer acts as a mediator that blocks substrate noise from reaching the sensitive CMOS circuit nodes, providing electromagnetic compatibility without requiring BJT components.
2Object-affected harmful factors
If conventional CMOS devices are used in a triple well flow with reverse-junction-isolation, then isolation from substrate noise is improved, but the reference voltage remains sensitive to temperature variations
Solution Approach 1:
The patent employs parameter changes by adjusting the gate lengths of transistors within the circuit to achieve zero temperature coefficient (ZTC) operation. By carefully selecting and tuning the gate length parameters of different transistors, the circuit compensates for temperature-induced voltage drift and achieves temperature-independent reference voltage output.
Solution Approach 2:
The patent implements feedback mechanisms through interconnected current mirrors and folded-cascode amplifier stages that automatically adjust operating points to maintain temperature stability. The feedback loops sense temperature-induced variations and compensate through controlled current adjustments, achieving ZTC without requiring external temperature sensing components.
3Temperature
If the gate length of transistors is adjusted to achieve zero temperature coefficient operation, then temperature independence is improved, but the circuit design complexity increases
Solution Approach 1:
The patent merges multiple functions into unified circuit blocks. The folded-cascode amplifier simultaneously provides high gain, impedance transformation, and temperature compensation. Current mirror structures combine current copying with temperature stabilization functions, reducing the need for separate compensation circuits and simplifying the overall design despite the precision gate length requirements.
Solution Approach 2:
The patent designs universal CMOS building blocks that perform multiple functions. The folded-cascode stage serves as both an amplifier and a temperature compensation element. The current mirrors provide both current copying and bias stabilization. These multi-functional blocks reduce overall circuit complexity compared to using separate dedicated circuits for each function.
Data Source
AI summary
Voltage reference circuits are provided. A voltage reference circuit includes a transistor, a flipped-gate transistor, a first current mirror unit, a second current mirror unit and an output node. The gate and the drain of the flipped-gate transistor are coupled to the gate and the drain of the transistor. The first current mirror unit is configured to provide a first current to the flipped-gate transistor and the mirroring current in response to a bias current. The second current mirror unit is configured to drain a second current from the transistor in response to the mirroring current. The output node is coupled to the source of the transistor and the second current mirror unit, and is configured to output a reference voltage.