Asymmetric CMOS Voltage Reference Circuit for Sub-1V Precision
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Solution Overview
Problem
Existing voltage reference circuits face challenges in achieving high precision and robustness, especially at low supply voltages below 1.0V, due to sensitivity to power supply noise, device noise, and circuit element mismatch, and often require extensive calibration.
Innovation Solution
A voltage reference circuit is designed using CMOS technology, comprising two asymmetric differential amplifiers with transistors of different threshold voltages and a resistor string with separate feedback loops to provide a reference voltage, which is temperature and process spread compensated.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If traditional bandgap reference circuits are used, then reference voltage can be generated, but they cannot operate at supply voltages below 0.9V due to insufficient voltage to bias bipolar junction transistors
Solution Approach 1:
The patent replaces bipolar junction transistors (traditional mechanical/electrical component) with MOS transistors that can operate at lower voltages. Specifically, the invention uses a first MOS transistor and a second MOS transistor with different threshold voltages to generate the reference voltage, eliminating the need for high supply voltage required by BJT biasing.
Solution Approach 2:
The patent changes the operating parameters by using MOS transistors with different threshold voltages (Vth1 and Vth2) instead of relying on bipolar transistor characteristics. The reference voltage is generated based on the difference in threshold voltages of MOS transistors, allowing operation at supply voltages below 0.9V while maintaining circuit reliability.
2Device complexity
If open-loop voltage reference circuits are used, then circuit complexity is reduced, but precision and performance deteriorate due to high sensitivity to power supply noise, device noise, and leakage currents
Solution Approach 1:
The patent implements a closed-loop feedback architecture where the reference voltage output is fed back to the input of the differential amplifier. The first asymmetric differential amplifier receives the reference voltage at its negative input terminal, creating a feedback loop that compensates for changes in the output voltage, thereby reducing sensitivity to power supply noise, device noise, and leakage currents while maintaining circuit precision.
3Measurement precision
If extensive calibration is performed to achieve high precision, then measurement precision is improved, but manufacturing time and complexity increase
Solution Approach 1:
The patent employs asymmetric differential amplifiers that inherently compensate for circuit element mismatches and temperature variations through their asymmetric transistor configurations. The first asymmetric differential amplifier uses a first MOS transistor and a second MOS transistor with different threshold voltages, creating an intrinsic compensation mechanism that eliminates the need for extensive external calibration processes.
Solution Approach 2:
The patent changes the circuit parameters by using transistors with specifically selected different threshold voltages and asymmetric configurations that provide automatic compensation for process variations and temperature drift. This parameter selection enables the circuit to achieve high precision without requiring time-consuming calibration steps during manufacturing or operation.
Data Source
Figure 1
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AI summary
A voltage reference circuit (1) comprises a first asymmetric differential amplifier (10) and a second asymmetric differential amplifier (20), each comprising two transistors (M1, M2; M1', M2') with different threshold voltages (Vth1, Vth2) as differential pair, a resistor string (30) arranged between an output (13) of the first asymmetric differential amplifier (10) and a supply terminal (VSS), the resistor string (30) comprising a first portion (R1, R2), a second portion (R3, R4) and a connecting circuit node (31) interposed between them, wherein an output (23) of the second asymmetric differential amplifier (20) is coupled to the connecting circuit node (31). The first portion (R1, R2) of the resistor string (30) is configured to provide a first feedback voltage (Vf1) that is fed back to input terminals (11, 12) of the first asymmetric differential amplifier (10), and the second portion (R3, R4) of the resistor string (30) is configured to provide a second feedback voltage (Vf2) that is fed back to input terminals (21, 22) of the second asymmetric differential amplifier (20). The voltage reference circuit (1) is configured to provide a reference voltage (Vref) at the output (13, 23) of the first (10) or the second asymmetric differential amplifier (20).