In-situ Wet Etching for CMOS High-k Dielectric Residue Removal
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Solution Overview
Problem
Conventional methods for fabricating CMOS devices with high-k dielectric layers and metal gate electrodes face challenges such as residue adherence, leading to poor yield and degraded performance due to polymers or other residues on the device surface.
Innovation Solution
An in-situ wet etching method is employed, using a first etching solution to remove cover layers and a mixed etching solution containing hydrochloric and hydrofluoric acids to etch the high-k dielectric and interfacial layers within the same etching machine, avoiding the need for multiple loading/unloading and reducing residue adherence, along with an optional plasma treatment to facilitate the etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple wet etching steps are performed with separate loading/unloading of the device, then each etching step can be optimized for specific layers, but polymer residues adhere to the device surface causing poor yield and degraded performance
Solution Approach 1:
The patent combines multiple separate wet etching steps into a single continuous etching process by keeping the device loaded in the etching machine throughout all etching operations. Different etching solutions are introduced sequentially without removing the device, thereby preventing polymer residue accumulation and eliminating the need for repeated loading/unloading cycles.
Solution Approach 2:
The etching process maintains continuous action by keeping the device continuously loaded in the etching machine throughout multiple etching steps. The useful action of etching proceeds without interruption, with only the etching solution being changed between steps, ensuring no polymer residues adhere to the device surface during transitions.
2Manufacturing precision
If multiple separate wet etching steps are performed, then different etching solutions can be used for different layers, but the fabrication process becomes complex with multiple loading/unloading operations
Solution Approach 1:
The patent merges multiple separate etching operations into a single integrated process within one etching machine. The device remains loaded throughout, and different etching solutions are sequentially introduced to target specific layers, thereby simplifying the overall fabrication process while maintaining layer-specific etching precision.
Solution Approach 2:
The etching machine is used universally for all etching steps by keeping the device loaded throughout the entire process. The same machine performs multiple etching functions with different solutions, eliminating the need for separate machines or repeated loading/unloading operations.
3Ease of manufacture
If conventional wet etching is performed with device removal between steps, then cleaning can be done, but polymer residues still adhere to the device surface
Solution Approach 1:
The etching process proceeds continuously without device removal, preventing polymer residues from adhering to the device surface during transitions between etching steps. The continuous action ensures no opportunity for residue accumulation occurs during loading/unloading cycles.
Solution Approach 2:
Different etching solutions act as intermediaries to selectively remove specific layers while preventing polymer residue adherence. The solutions are sequentially introduced without device removal, allowing each solution to perform its specific etching function while maintaining a residue-free device surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances etching efficiency, simplifies the fabrication process, and prevents residue adherence, thereby improving yield and device performance by directly replacing etching solutions and integrating seamlessly with general CMOS fabrication processes.
Implementation Method 1
two wet etching steps are performed to form gate dielectric layers of the MOS devices
Implementation Method 2
using a diluted hydrofluoric acid (HF) as etching solution, etching the hafnium oxide layer 110 and the silicon oxide layer 108
Implementation Method 3
an optional plasma treatment to facilitate the etching process
Data Source
AI summary
A method of fabricating a MOS device comprises steps as follows: An interfacial layer, a high-k dielectric layer and a cover layer on a substrate are sequentially formed. Then an in-situ wet etching step is performed by sequentially using a first etching solution to etch the cover layer and using a second etching solution to etch the high-k dielectric layer and the interfacial layer until the substrate is exposed, wherein the second etching solution is a mixed etching solution containing the first etching solution.