CMOS Write Driver Architecture for High-Voltage Magnetic Recording
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Solution Overview
Problem
Existing data storage devices face challenges in achieving high-speed and high-voltage write operations efficiently, with BiCMOS processes being costly and less efficient compared to all-CMOS solutions.
Innovation Solution
A high-speed high-voltage CMOS write driver architecture utilizing all-CMOS processes with high-voltage devices, incorporating low and high voltage CMOS devices in a preamplifier circuit to generate write currents for magnetic media, including a write driver with a data switch section and stationary cascode section.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BiCMOS processes are used to achieve high-speed and high-voltage write operations, then performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent changes the voltage parameter by introducing a high voltage domain (VHV) separate from the low voltage domain (VLV). High voltage CMOS devices operate at VHV for write operations while low voltage CMOS devices operate at LVV for control logic, allowing high-voltage performance without requiring expensive BiCMOS processes. This parameter separation enables cost-effective high-speed write operations.
Solution Approach 2:
The write driver circuit is segmented into distinct high voltage CMOS devices and low voltage CMOS devices. The high voltage section handles the power-intensive write current generation, while the low voltage section handles control and timing. This segmentation allows each section to be optimized independently using appropriate voltage domains, achieving high performance at lower cost than BiCMOS.
2Ease of manufacture
If all-CMOS processes are used instead of BiCMOS, then manufacturing cost decreases, but achieving high-speed and high-voltage performance becomes more difficult
Solution Approach 1:
The patent introduces high voltage CMOS devices that operate at elevated voltage levels within the all-CMOS process framework. By changing the voltage parameter and creating a high voltage domain, the circuit achieves high-speed write operations comparable to BiCMOS while maintaining the cost advantages of all-CMOS manufacturing. The high voltage operation enables faster switching and higher current drive capability.
3Ease of manufacture
If high voltage devices are integrated into CMOS process, then cost advantage is maintained, but device complexity increases
Solution Approach 1:
The circuit is divided into clearly defined high voltage CMOS device sections and low voltage CMOS device sections. Each section has dedicated functionality - high voltage devices handle power-intensive operations while low voltage devices handle control. This segmentation manages complexity by creating modular, functionally-separated blocks that can be designed and analyzed independently, rather than attempting to optimize a monolithic high-voltage CMOS circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CMOS write driver achieves high-speed and high-voltage write operations at a lower cost than BiCMOS, providing equivalent or better performance with a cost advantage and improved efficiency.
Implementation Method 1
The write driver generates analog write current pulses that are applied to the inductive coil in the write head to write data by selectively magnetizing the magnetic media of the recording layer on the disk
Implementation Method 2
the magnetic transitions are sensed by a read element (e.g., a magneto-resistive element) and the resulting read signal is demodulated by a suitable read channel
Data Source
AI summary
A data storage device comprises a magnetic medium and a head configured to be actuated over the magnetic medium. The head comprises a write element and a write driver configured to generate a write current to be applied to the write element. The write driver comprises a data switch section configured to switchably output low-level signals and high-level signals, and a stationary cascode section configured to receive the low-level signals and high-level signals from the data switch section and to generate a cascode pass through current. The data switch section comprises low voltage CMOS devices and the stationary cascode section comprises high voltage CMOS devices.