CMOS 3-Input XNOR/OR Gate Layout for Lower Leakage
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Solution Overview
Problem
Conventional XOR and XNOR gate circuits in CMOS transistor technology face issues with significant leakage and area occupancy, particularly in 3-input XNOR gate circuits, which require inverted input signals and result in increased layout area due to diffusion breaks and input capacitance variations.
Innovation Solution
A CMOS transistor circuit design that implements XOR and XNOR functions using a series of interconnected blocks, including NOR, AND-OR, and OR-AND gates, along with an inverter gate, to generate output signals corresponding to various logic states, eliminating the need for transmission gates and input inverters, thereby reducing leakage and area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 3-input XNOR gate circuit is used, then the circuit can implement XNOR function, but the leakage is significant and area occupancy is large
Solution Approach 1:
The conventional 3-input XNOR gate is segmented into multiple 2-input XNOR gates and inverters arranged in a specific topology. This segmentation allows for reduced leakage by eliminating transmission gates while maintaining the XNOR function through a series of standard CMOS gates with controlled signal flow paths.
Solution Approach 2:
The patent inverts the input signals directly at the gate level without requiring separate input inverters. By inverting inputs A and B within the gate structure itself, the circuit eliminates the need for external input inversion stages, reducing overall area and leakage while maintaining correct XNOR logic operation.
2Reliability
If conventional 3-input XNOR gate circuit is used, then the circuit can implement XNOR function, but the area occupancy is large due to diffusion breaks and input capacitance variations
Solution Approach 1:
The patent extracts and eliminates the transmission gate component from the conventional XNOR circuit. By removing this component, the circuit avoids diffusion breaks and associated layout complexity, significantly reducing area occupancy while maintaining XNOR functionality through alternative CMOS gate configurations.
Solution Approach 2:
The patent designs a universal XNOR gate structure that can handle multiple input conditions (A, B, C) using a standardized arrangement of 2-input XNOR gates and inverters. This universal topology provides consistent area usage regardless of input capacitance variations, eliminating the need for area compensation due to capacitive effects.
3Reliability
If conventional 3-input XNOR gate circuit is used, then the circuit requires inverted input signals, but this increases area due to additional inverters
Solution Approach 1:
The patent merges the input inversion function directly into the XNOR gate structure itself. By integrating inverters within the gate logic paths rather than as separate external components, the circuit achieves signal inversion without adding extra area, as the inversion is performed in-place during the logic operation.
Solution Approach 2:
The patent performs input signal inversion as a preliminary action within the gate structure before the main XNOR operation. By pre-inverting inputs A and B inside the gate, the circuit eliminates the need for separate external inverter stages, reducing overall area while ensuring correct logic operation from the outset.
Data Source
AI summary
A CMOS transistor circuit including: a first block generating a first output signal of a NOR state, in response to first and second input signals; a second block including a first AND-OR gate, the second block generating a second output signal of an OR or an AND state, the second block receiving the first and second input signals and the first output signal; a third block generating a third output signal of the NOR state, in response to a third input signal and the second output signal; a fourth block including a second AND-OR gate, the fourth block generating a fourth output signal of the OR or the AND state in response to the third input signal, the second output signal and the third output signal; and a fifth block including an inverter gate, the fifth block generating a fifth output signal in response to the fourth output signal.