CMOSFET Gate Stack with Metal Interlayer for Threshold Voltage Control
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Solution Overview
Problem
Current CMOS devices with high-k gate dielectric/metal gate configurations face challenges in controlling threshold voltages due to limited adjustment capabilities caused by phenomena like Fermi level pinning and flat band voltage roll-off, especially in optimizing NMOS and PMOS devices to have substantially equal and reduced threshold voltages.
Innovation Solution
A CMOSFET device with a gate stack configuration where very thin metal layers are deposited between high-k gate dielectric layers in NMOS and PMOS regions, generating positive or negative charges and interface dipoles through thermal diffusion of metal atoms to adjust flat band voltage and control threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional high-k gate dielectric/metal gate configuration is used, then leakage current is reduced, but threshold voltage control capability is limited
Solution Approach 1:
The gate dielectric layer is segmented into multiple layers (first high-k gate dielectric layer, second high-k gate dielectric layer) with a metal layer inserted between them. This segmentation allows independent control of threshold voltage through the metal layer while maintaining the low leakage current properties of the high-k dielectric structure.
Solution Approach 2:
A metal layer is introduced as an intermediary between the two high-k gate dielectric layers. This metal layer acts as a mediator to adjust the flat band voltage and control the threshold voltage through interface dipoles and charge generation, without compromising the low leakage current characteristic of the high-k dielectric configuration.
2Adaptability or versatility
If metal gate materials with different band-edge work functions are used, then threshold voltage adjustment is possible, but adjustment range is limited due to Fermi level pinning effect
Solution Approach 1:
The invention changes the parameters of the gate stack by introducing a metal layer between high-k dielectric layers. This allows control of threshold voltage through variations in metal layer thickness, material composition, and position, enabling adjustment beyond the limitations of Fermi level pinning in conventional metal gate materials.
Solution Approach 2:
The gate stack is designed as a composite structure combining multiple high-k gate dielectric layers with a metal layer. This composite configuration enables threshold voltage control through the combined effects of interface dipoles at multiple interfaces and charges in the metal layer, extending the adjustment range beyond what single metal gate materials can achieve.
3Adaptability or versatility
If high-k dielectric cap layer is introduced to generate interface dipoles, then threshold voltage control is improved, but flat band voltage roll-off effect limits effectiveness
Solution Approach 1:
The gate dielectric is segmented into multiple high-k layers with a metal layer inserted between them. This segmentation creates multiple interfaces that generate interface dipoles, enhancing threshold voltage control capability while the distributed structure mitigates the flat band voltage roll-off effect.
Solution Approach 2:
The composite structure of multiple high-k dielectric layers combined with a metal layer creates multiple interface dipole regions. This composite configuration enhances threshold voltage control through cumulative interface dipole effects while improving flat band voltage stability by distributing the electrical characteristics across multiple interfaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively enhances interface dipoles and controls fixed charges within high-k gate dielectric layers, allowing precise control of threshold voltage in CMOS devices, thereby improving the balance and reduction of threshold voltages for NMOS and PMOS devices.
Implementation Method 1
interface dipoles caused by thermal diffusion of the metal atoms
Implementation Method 2
the first metal layer is deposited between two or more high-k gate dielectric layers of the same or different types by means of physical deposition
Implementation Method 3
the first metal layer is deposited between two or more high-k gate dielectric layers of the same or different types by means of physical deposition, chemical vapor deposition, or atom layer deposition
Implementation Method 4
the first metal layer is deposited between two or more high-k gate dielectric layers of the same or different types by means of physical deposition, chemical vapor deposition, or atom layer deposition
Data Source
AI summary
There is provided a CMOSFET device with a threshold voltage controlled by means of its gate stack configuration and a method of fabricating the same. The CMOSFET device comprises: a semiconductor substrate; am interface layer grown on the silicon substrate; a first high-k gate dielectric layer deposited on the interface layer; a very thin metal layer deposited on the first high-k gate dielectric layer; a second high-k gate dielectric layer deposited on the very thin metal layer; and a gate electrode layer deposited on the second high-k gate dielectric layer.