3D Semiconductor Via Plug Support Pattern for CMP Dishing
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Solution Overview
Problem
The increasing integration of semiconductor devices leads to challenges in vertically aligning fine contact plugs with large aspect ratios, and the CMP process causes dishing issues affecting the flatness and alignment between contact plugs.
Innovation Solution
The implementation of support patterns that contact the side surface of lower via plugs, which are coplanar with their top surfaces, helps alleviate dishing and improves alignment margins by acting as a CMP stopper or resistor, ensuring the lower via plugs and upper via plugs remain electrically connected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple CMP processes are performed to achieve fine pitch and space between interconnections and contact plugs, then manufacturing precision is improved, but dishing occurs causing flatness degradation and alignment issues
Solution Approach 1:
The support pattern is formed in advance before the CMP process, serving as a predetermined structural element that will counteract dishing during subsequent CMP operations. This preliminary structure is designed to maintain surface flatness throughout the manufacturing process
Solution Approach 2:
The support pattern acts as an intermediary element between the contact plug and the CMP process. It provides mechanical support and distributes CMP pressure, preventing direct damage to the contact plug surface and maintaining alignment precision without compromising flatness
2Productivity
If the pitch and space between interconnections and contact plugs are reduced for higher integration, then device density is improved, but alignment difficulty between fine contact plugs increases
Solution Approach 1:
The support structure is segmented into multiple support patterns distributed across the substrate, each providing localized alignment assistance. This segmentation allows precise control over individual contact plug positions while maintaining overall high device density
Solution Approach 2:
The support pattern extends in the horizontal dimension to provide broader alignment reference for vertically aligned contact plugs. By creating a lateral support structure, the patent transforms a vertical alignment problem into a two-dimensional positioning solution, improving alignment precision without reducing pitch
Data Source
AI summary
The semiconductor device includes a substrate having a cell area and a via area; a transistor and a logic interconnection disposed over the substrate; a lower insulating layer covering the transistor and the logic interconnection; a lower conductive layer on the lower insulating layer in the cell area; a support pattern disposed on the lower insulating layer in the via area; a lower via plug having a side surface in contact with the support pattern and a bottom surface in contact with the logic interconnection; a word line stack disposed on the lower conductive layer in the cell area; an dielectric layer stack disposed on the support pattern in the via area; a vertical channel pillar penetrating the word line stack to be connected to the lower conductive layer; and an upper via plug penetrating the dielectric layer stack to be vertically aligned with the lower via plug.