Semiconductor Light-Emitting Structure With CMP-Flat Reflector Layers
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Solution Overview
Problem
Conventional methods for manufacturing semiconductor light-emitting devices, such as VCSELs, face challenges with chemical mechanical polishing (CMP) dishing, leading to strain and level differences between membrane reflectors and their periphery, which can hinder junction formation and device reliability.
Innovation Solution
A method involving the formation of a patterned dielectric layer, a high refractive index layer, and a periodic structure with chemical mechanical polishing to ensure coplanarity between the mask and low refractive index layers, facilitating efficient heat dissipation and reducing strain by maintaining the bonding interface stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing (CMP) is used to planarize the membrane reflector portion, then the surface flatness is improved, but dishing occurs causing level differences between the membrane reflector portion and its periphery
Solution Approach 1:
The patent divides the membrane reflector structure into multiple layers (first membrane reflector layer, second membrane reflector layer, third membrane reflector layer) with different materials and functions. This segmentation allows each layer to address specific issues: the first layer provides base reflectivity, the second layer (with through-holes) enables stress relief and planarization, and the third layer provides final optical performance, thereby resolving the contradiction between achieving surface flatness and avoiding dishing-induced level differences.
Solution Approach 2:
The patent applies different materials and structures to different regions of the membrane reflector. Specifically, the second membrane reflector layer contains through-holes in certain regions to reduce stress and prevent dishing, while other regions maintain continuous reflective material. This local variation in structure allows the device to achieve both surface flatness through CMP and maintain proper stress distribution to prevent level differences.
2Reliability
If a III-V junction is formed in the membrane reflector portion, then optical performance is improved, but strain is generated due to dishing
Solution Approach 1:
The patent performs preliminary stress relief by forming the second membrane reflector layer with through-holes before forming the III-V junction. This preliminary action removes excess stress from the structure, creating a more favorable stress state for subsequent junction formation. By addressing the stress issue before creating the III-V junction, the patent enables high optical performance without generating harmful strain in the junction region.
3Manufacturing precision
If the dishing amount is large, then CMP planarization appears effective, but the junction becomes impossible to form
Solution Approach 1:
The patent incorporates a stress-compensating structure (the second membrane reflector layer with through-holes) beforehand to cushion against the dishing effect. This preliminary stress management ensures that even when CMP achieves significant planarization, the underlying stress distribution remains favorable for junction formation. The cushioning structure prevents the dishing-induced stress from reaching levels that would make junction formation impossible.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and stability of semiconductor light-emitting devices by minimizing strain and ensuring close contact between the optical semiconductor structure and the substrate, improving heat dissipation and maintaining device performance across temperature changes.
Implementation Method 1
performing chemical mechanical polishing to cause the mask layer and the low refractive index layer to form substantially the same plane
Data Source
AI summary
According to one embodiment, the first process of forming a first light-reflecting structure including forming a patterned dielectric layer on a substrate, forming a first high refractive index layer on the substrate and the dielectric layer, planarizing the first high refractive index layer, forming a mask layer on the first high refractive index layer, forming a periodic structure in the mask layer and the first high refractive index layer, the periodic structure having openings separated at a constant period, forming a low refractive index layer on the mask layer and filling the periodic structure with the low refractive index layer, and performing chemical mechanical polishing to cause the mask layer and the low refractive index layer to form substantially the same plane.