CMP-Free III-V Isolation Using Dielectric Spacers
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Solution Overview
Problem
The challenge lies in forming effective isolation structures for III-V compound semiconductor FETs, as existing methods used for silicon-based technologies are not compatible, particularly due to the difficulty in performing high temperature oxidation and chemical mechanical planarization processes with III-V compound semiconductors.
Innovation Solution
A semiconductor structure is developed with a III-V compound semiconductor channel material on a mesa portion of a substrate, featuring a dielectric spacer structure on its sidewalls and an isolation structure formed on these spacers, avoiding the use of high temperature oxidation and chemical mechanical planarization processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If field oxide isolation structures are formed using high temperature oxidation process, then isolation structures can be formed for silicon based technologies, but the process cannot be performed with III-V compound semiconductors
Solution Approach 1:
The patent changes the temperature parameter of the oxidation process from high temperature (incompatible with III-V) to low temperature (compatible with III-V), enabling the same isolation structure formation approach to work with different semiconductor materials
Solution Approach 2:
The patent introduces a sacrificial layer as an intermediary material that enables isolation structure formation without requiring high temperature oxidation of the III-V channel material itself. The sacrificial layer is oxidized at low temperature to create the isolation structures
Data Source
AI summary
A semiconductor structure is provided that includes a channel material portion composed of a III-V compound semiconductor located on a mesa portion of a substrate. A dielectric spacer structure is located on each sidewall surface of the channel material portion and each sidewall surface of the mesa portion of the substrate. The dielectric spacer structure has a height that is greater than a height of the channel material portion. An isolation structure is located on each dielectric spacer structure, wherein a sidewall edge of the isolation structure is located between an innermost sidewall surface and an outermost sidewall surface of the dielectric spacer structure.