CMP Apparatus with Negative Voltage Polishing Pad
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing chemical mechanical planarization (CMP) process often results in residual silicon oxide particles on the wafer and polishing pad, leading to surface scratches and unevenness, which affect semiconductor device performance and production efficiency.
Innovation Solution
The CMP apparatus incorporates a polishing pad with a metal layer connected to a negative power source and an alkaline solution supply to create a negative interface potential, preventing silicon dioxide particles from being absorbed and promoting their removal, thereby reducing residue formation and improving planarization results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional CMP process is used, then planarization is achieved, but residual silicon oxide particles are formed on wafer and polishing pad causing scratches and unevenness
Solution Approach 1:
The patent replaces the conventional mechanical removal of polishing particles with an electrostatic field-based removal mechanism. By applying a negative voltage to the polishing pad, an electrostatic field is generated that actively repels negatively charged silicon oxide particles, preventing their adhesion to the pad surface and enabling their continuous removal during the CMP process.
Solution Approach 2:
The patent changes the electrical parameter of the polishing pad by applying a negative voltage (electrostatic field), which fundamentally alters the interaction between the pad surface and polishing particles. This parameter change transforms the surface from a passive mechanical interface to an active electrostatic field that controls particle adhesion and removal.
2Manufacturing precision
If polishing particles are used for planarization, then surface flatness is improved, but particle residue on polishing pad leads to scratches on wafer
Solution Approach 1:
The patent substitutes the mechanical retention of particles on the pad with an electrostatic repulsion mechanism. The negative voltage creates an electrostatic field that continuously pushes polishing particles away from the pad surface, preventing them from being mechanically retained and subsequently transferred to the wafer as scratches.
Solution Approach 2:
The patent converts the naturally negative charge of silicon oxide particles, which normally causes them to adhere to the pad, into a beneficial effect. By applying a negative voltage to the pad, the same negative charge property is used to create repulsion, turning the particles' inherent characteristic from a source of adhesion problems into a mechanism for their active removal.
3Productivity
If traditional CMP apparatus is used, then polishing function is provided, but additional cleaning functions require separate equipment and processes
Solution Approach 1:
The patent makes the polishing pad multi-functional by integrating both polishing and particle removal capabilities into a single component. The pad not only provides the mechanical polishing function through its contact with the wafer but also simultaneously performs particle removal through the electrostatic field generated by the applied negative voltage.
Solution Approach 2:
The patent merges the polishing function and the particle removal function into a single integrated process and apparatus. The electrostatic field generation system is combined with the polishing pad structure, allowing both functions to operate simultaneously during the CMP process without requiring separate cleaning equipment or steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents the formation of residual polishing particles on the wafer and polishing pad, enhancing the CMP process by ensuring better surface uniformity and reducing the risk of scratches, thus improving the quality and efficiency of semiconductor manufacturing.
Implementation Method 1
a negative power source configured to apply a negative voltage onto a surface of the polishing pad
Implementation Method 2
a polishing slurry supply tube configured to provide a polishing slurry for a CMP process; a basic solution supply port configured to supply a basic solution onto a surface of the polishing pad
Implementation Method 3
When the platen is rotated by an electrical motor, the polishing head is also rotated by the clamping fixture with a same direction as the platen
Implementation Method 4
During the CMP process, the polishing slurry flows away from the edge of the polishing pad under the centrifuge force
Data Source
AI summary
A chemical mechanical planarization (CMP) apparatus is provided. The CMP apparatus includes at least one platen; and a polishing pad disposed on the platen. The CMP apparatus also includes a polishing head disposed above the platen and configured to clamp a to-be-polished wafer; and a basic solution supply port disposed above the platen and configured to supply a basic solution onto a surface of the polishing pad. Further, the CMP apparatus includes a slurry arm disposed above the platen and configured to supply a polish slurry on the surface of the polishing pad; and a deionized water supply port configured to supply deionized water onto the surface of the polishing pad. Further, the CMP apparatus also includes a negative power source configured to apply a negative voltage onto the surface of the polishing pad.


