CMP Thickness Control via Per-Wafer Measurement
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Solution Overview
Problem
Conventional chemical mechanical polishing (CMP) processes face challenges in precisely controlling the thickness of semiconductor elements, leading to high yield loss and production costs due to reliance on feedback control systems and imprecise polishing time estimation, resulting in either over or under polishing issues.
Innovation Solution
A method and system for CMP that measure and determine specific polishing parameters for each semiconductor element based on its dimensions, eliminating the need for feedback control by using a measuring device, determining device, and polishing device to apply tailored polishing recipes for precise thickness control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If feedback control is used to estimate polishing time by sampling wafers, then polishing time can be adjusted, but yield loss increases and production cost increases
Solution Approach 1:
The patent measures the thickness of each wafer before polishing in advance, and determines the polishing time for each wafer individually based on its measured thickness. This preliminary measurement and customization of polishing parameters for each wafer eliminates the need for post-polishing feedback adjustment, thereby preventing yield loss while achieving precise thickness control.
2Manufacturing precision
If feedback control is used to estimate polishing time by sampling wafers, then polishing time can be adjusted, but production cost increases
Solution Approach 1:
The patent implements preliminary thickness measurement for each wafer before polishing, allowing the system to determine optimal polishing time in advance. This eliminates the need for complex feedback control systems and repeated sampling, thereby reducing production costs while maintaining precise thickness control.
3Ease of operation
If the same estimated polishing time is provided for all wafers in one lot, then process is simple, but thickness control precision is insufficient
Solution Approach 1:
The patent applies local quality by measuring the thickness of each wafer individually and determining customized polishing time for each wafer based on its specific thickness. This individualized approach ensures that each wafer receives the precise polishing treatment it needs, achieving high thickness control precision while maintaining operational simplicity through automated per-wafer parameter determination.
4Manufacturing precision
If polishing time is extended to ensure complete metal removal, then under polish is avoided, but over polish occurs and resistance increases
Solution Approach 1:
The patent dynamically changes the polishing time parameter for each wafer based on its measured thickness. By customizing the polishing time to match the actual thickness of each wafer, the system ensures complete metal removal without over-polishing, thereby preventing both under-polish and over-polish conditions while optimizing the polishing process parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces yield loss and optimizes product quality by ensuring precise thickness control and uniformity across multiple lots, reducing the complexity of the CMP system and enhancing the accuracy of the polishing process.
Implementation Method 1
obtaining the respective dimension of the each semiconductor element
Implementation Method 2
a chemical mechanical polishing (CMP) process, by which the surface of the wafer is pressed on a polishing pad having polishing materials thereon
Data Source
AI summary
A chemical mechanical polishing method is provided. The chemical mechanical polishing method includes steps of providing a plurality of semiconductor elements to be polished, obtaining a respective dimension of the each semiconductor element to be polished, and polishing the each semiconductor element according to the respective dimension thereof.