CMP Pixel Electrode Formation in Thin Film Transistor Array Panels

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The manufacturing of thin film transistor array panels is hindered by the complexity and cost of multiple lithography steps required in the layered structure formation, particularly in forming conductive and insulating layers for display devices like LCDs and OLEDs.

Innovation Solution

A method involving the formation of thin film transistors with a gate electrode, source electrode, and drain electrode on a substrate, followed by a passivation layer, photoresist film, and CMP process to form pixel electrodes connected to the drain electrode, which simplifies the process by reducing the number of lithography steps through the use of photoresist films with varying thicknesses and contact holes for precise etching and conductive film deposition.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If multiple lithography steps are used to form conductive and insulating layers, then the structural integrity and precision of the TFT array panel is improved, but the manufacturing time and cost increase

Engineering Contradiction:

Improvestructural integrityVSAvoidmanufacturing time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent combines the formation of pixel electrodes and contact assistants into a single lithography step by forming a conductive film that covers both the drain electrode and the pixel electrode formation area, then using one etching process to define both structures simultaneously. This merging of operations reduces the total number of lithography steps while maintaining the required structural precision.

Inventive Principle:

Principle #5Merging (Combining)

2Manufacturing precision

If multiple lithography steps are used to form conductive and insulating layers, then the manufacturing precision of the TFT array panel is improved, but the manufacturing cost increases

Engineering Contradiction:

Improvestructural integrityVSAvoidmanufacturing cost

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent merges multiple lithography operations into a single step by designing a conductive film pattern that serves dual purposes: forming both the pixel electrode and the contact assistant structures. This consolidation reduces the number of expensive lithography steps required while maintaining the necessary manufacturing precision for the TFT array panel.

Inventive Principle:

Principle #5Merging (Combining)

3Productivity

If a CMP process is used to form pixel electrodes, then the number of lithography steps is reduced, but the manufacturing process complexity increases

Engineering Contradiction:

Improvenumber of lithography stepsVSAvoidmanufacturing process complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent replaces traditional mechanical lithography and etching operations with a chemical mechanical polishing (CMP) process to form the pixel electrode. The CMP process uses a combination of chemical etching and mechanical polishing to selectively remove the conductive film, replacing the need for multiple lithography steps while managing process complexity through controlled chemical reactions.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Manufacturing precision

If photoresist films with varying thicknesses are used, then the precision of etching and conductive film deposition is improved, but the ease of manufacture decreases

Engineering Contradiction:

Improveetching precisionVSAvoidprocess simplicity

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent applies local quality by using photoresist films with varying thicknesses in different areas of the substrate. Thinner photoresist is applied where precise etching is needed for contact holes, while thicker photoresist is used in areas requiring broader coverage for pixel electrode formation. This spatial variation in photoresist thickness optimizes etching precision for different structural requirements.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach simplifies the manufacturing process by integrating pixel electrode and contact assistant formation into a single lithography step, reducing manufacturing time and cost while maintaining the structural integrity and electrical connectivity of the TFT array panel.

Implementation Method 1

removing the photoresist film and the conductive film disposed on the photoresist film using a CMP (chemical mechanical polishing) process

Methodology Applied

Scientific EffectChemical mechanical polishing:

Data Source

PatentUS7541225B2Method of manufacturing a thin film transistor array panel that includes using chemical mechanical polishing of a conductive film to form a pixel electrode connected to a drain electrode

Publication Date: 2009.06.02 SAMSUNG DISPLAY CO LTD

AI summary

A method of manufacturing a thin film transistor array panel is provided, the method including forming a thin film transistor having a gate electrode, a source electrode, and a drain electrode on a substrate, forming a passivation layer on the source electrode and the drain electrode, forming a photoresist film on the passivation layer, selectively etching the passivation layer using the photoresist film as a mask, forming a conductive film, and removing the photoresist film along with the conductive film disposed on the photoresist film using a CMP (chemical mechanical polishing) process to form a pixel electrode being connected to the drain electrode.