CMP Planarization for Non-Volatile Memory Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for forming non-volatile memory cells using nitride trap memory result in chemical damage due to the use of corrosive acids, leading to increased random single bit (RSB) failure rates and reduced yield.
Innovation Solution
A chemical mechanical polishing (CMP) process is employed to planarize the oxide layer between memory cells, eliminating the need for acidic etching and minimizing chemical damage, by using a ceria-based slurry with high selectivity to determine the endpoint of the polishing process and ensuring precise removal of the oxide layer without damaging the polysilicon layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If corrosive acids (hydrofluoric acid and phosphoric acid) are used to etch and remove oxide layers, then the oxide layer can be removed effectively, but chemical damage occurs on the substrate leading to increased RSB failure rate and reduced yield
Solution Approach 1:
The patent changes the fundamental parameter of the etching process from chemical etching using corrosive acids to mechanical polishing using CMP technology. This parameter change eliminates the chemical damage caused by acid etching while achieving effective oxide layer removal, thereby reducing RSB failure rate and improving yield.
Solution Approach 2:
The patent replaces the chemical etching system (using hydrofluoric acid and phosphoric acid) with a mechanical polishing system (CMP process). This substitution eliminates the harmful chemical interactions that cause substrate damage and RSB failures while maintaining the capability to remove oxide layers effectively.
2Ease of manufacture
If phosphoric acid is used for lift-off process, then silicon nitride layer can be removed completely, but the substrate surface becomes damaged and yield is reduced
Solution Approach 1:
The patent changes the removal method from chemical etching with phosphoric acid to mechanical polishing with CMP. This parameter change preserves the substrate surface quality by eliminating the chemical damage and cracking that occur during acid-based lift-off, while still achieving complete silicon nitride layer removal.
Solution Approach 2:
The patent substitutes the chemical lift-off process using phosphoric acid with a mechanical polishing process. This substitution prevents the substrate surface damage, cracking, and contamination that occur during acid exposure, thereby improving manufacturing precision and yield.
3Ease of manufacture
If BD oxide layer is etched by hydrofluoric acid, then the oxide layer between gate structures is removed, but weak interfaces are generated and chemical damage occurs
Solution Approach 1:
The patent changes the etching parameter from chemical etching with hydrofluoric acid to mechanical polishing with CMP. This change eliminates the interface weakening caused by chemical etching while achieving effective oxide layer removal, thereby maintaining interface strength and reducing chemical damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CMP process significantly reduces chemical damage, improves the random single bit (RSB) failure rate, and increases the yield of non-volatile memory cells by achieving a flatter oxide layer without the use of corrosive acids.
Implementation Method 1
performing a chemical mechanical polishing (CMP) process to remove the oxide layer over the stacking units and outside the aperture
Data Source
AI summary
A method of forming a non-volatile memory cell is provided. The method comprises: (a) providing a substrate; (b) forming a stacking structure on the substrate, the stacking structure at least comprising an oxide-nitride-oxide layer (ONO layer) and a polysilicon layer thereon; (c) patterning the stacking structure to form a plurality of separated stacking units, each two stacking units having an aperture therebetween; (d) forming a source region and a drain region buried in the substrate at two sides of the each stacking unit; (e) forming an oxide layer in the aperture and over the stacking units; and (f) performing a chemical mechanical polishing (CMP) process to remove the oxide layer over the stacking units and outside the aperture.