CMP-Friendly Polymer Coatings for Planar Recessing Variable-Height Layers
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Solution Overview
Problem
Integrated circuit manufacturing processes face challenges in achieving planar recessing of topographically variable materials, particularly in replacement gate processes, where variations in thickness and height across the chip surface complicate the removal of layers without damaging underlying materials or causing charge carrier depletion.
Innovation Solution
A method involving the application of a monomer-containing solvent solution, followed by pre-baking and baking to form a stable polymer coating, which is then planarized through chemical mechanical polishing (CMP) and etching, allowing for top-down recessing of materials to a target height while maintaining the integrity of underlying layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional gate materials are used, then manufacturing process is simpler, but device density and capacitance are insufficient
Solution Approach 1:
The gate structure is segmented into multiple functional layers: a dummy gate layer formed first, then removed to create trenches, which are subsequently filled with high-k dielectric material and metal gate materials. This segmentation allows each layer to be optimized independently for its specific function while maintaining overall device performance
Solution Approach 2:
A dummy gate stack is formed preliminarily before source and drain regions are created. This preliminary structure guides subsequent processing steps and enables proper alignment of high-k dielectric and metal gate layers during the replacement gate process
2Reliability
If annealing is applied to source and drain regions, then electrical properties improve, but work function of electrode metals shifts undesirably
Solution Approach 1:
Source and drain regions are formed and annealed while the dummy gate structure is still in place. This preliminary formation occurs before the final metal gate materials are deposited, protecting the electrode metals from annealing-induced work function shifts while still enabling proper source and drain electrical characteristics
Solution Approach 2:
The dummy gate structure serves as an intermediary element that enables source and drain annealing without directly exposing the final metal gate materials to high temperatures. It acts as a protective placeholder that can be removed after serving its guiding function
3Manufacturing precision
If CMP is used to planarize surfaces, then surface uniformity improves, but underlying materials may be damaged
Solution Approach 1:
A polymer coating is applied as an intermediary protective layer over the high-k dielectric and metal gate structures before CMP processing. This coating acts as a sacrificial cushion that absorbs mechanical stress during polishing, preventing direct contact between the CMP pad and the underlying sensitive materials
Solution Approach 2:
The polymer coating is deposited beforehand to provide a cushioning layer that protects underlying materials from CMP-induced damage. This pre-applied protective layer is designed to be removed after serving its protective function, having already absorbed the mechanical stresses of the polishing process
4Reliability
If variable-height layers are recessed, then device density increases, but uniformity of recess depth becomes difficult to control
Solution Approach 1:
The polymer coating serves as a uniform intermediary layer over variable-height underlying structures. During CMP and etching processes, this coating provides a consistent reference plane that enables uniform recess depth control, as the coating thickness can be precisely controlled during deposition regardless of the underlying topography
Solution Approach 2:
The polymer coating undergoes parameter changes through controlled deposition thickness and selective removal. By adjusting the coating thickness parameter and using selective etching, uniform recess depths can be achieved across variable-height regions, transforming the topography while maintaining precise depth control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient planar recessing of materials with high selectivity, minimizing damage to underlying layers and achieving uniformity in CMP and etch rates, thereby facilitating the formation of highly planar surfaces and maintaining the structural integrity of integrated circuit devices.
Implementation Method 1
heating the wafer to within a first temperature range, maintaining the wafer within the first temperature range while the majority of the solvent evaporates from the solution
Implementation Method 2
heating the wafer to within a second temperature range that is above the first temperature range, then maintaining the wafer within the second temperature range until the monomers have polymerized to form a polymer coating
Implementation Method 3
CMP removes a first portion of the polymer
Implementation Method 4
etching removes a second portion of the polymer and effectuates a top-down recessing of the polymer
Data Source
AI summary
A method of manufacturing an integrated circuit device is provided. A first feature, which has a first susceptibility to damage by chemical mechanical processing (CMP), is formed at a first height as measured from an upper surface of the substrate. A second feature, which has a second susceptibility to damage by the CMP, is formed at a second height as measured from the upper surface of the substrate and is laterally spaced from the first feature by a recess. The second height is greater than the first height, and the second susceptibility is less than the first susceptibility. A sacrificial coating is formed in the recess over an uppermost surface of the first feature. CMP is performed to remove a first portion of the sacrificial coating and expose an upper surface of the second feature while leaving a second portion of the sacrificial coating in place over the first feature.