CMP Slurry Optimization for Polysilicon Integration
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Solution Overview
Problem
Current methods for integrating flash memory cells and MOS transistors face issues due to defects induced by the oxide cap layer, leading to non-uniformity and performance degradation in semiconductor devices.
Innovation Solution
A method involving a substrate with defined memory and periphery regions, forming a memory cell, a first polysilicon layer, a patterned cap layer, and a second polysilicon layer, followed by a chemical mechanical polishing process with an abrasive greater than 13% and a remove rate of less than 30 Angstroms/second to improve integration and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an oxide cap layer is sandwiched between two polysilicon layers before patterning, then the integration of flash memory cells and MOS transistors is achieved, but defects are induced between control gates and uniformity is lowered
Solution Approach 1:
The patent removes the oxide cap layer from between the polysilicon layers, extracting the harmful element that causes defects. This is achieved by adjusting the CMP process to selectively remove the oxide cap layer while maintaining the polysilicon layers, thereby eliminating the source of defects between control gates while preserving the integrated structure
Solution Approach 2:
The patent modifies the CMP process parameters, specifically using a slurry with pH between 9-11 and controlling the remove rate, to achieve selective removal of the oxide cap layer. This parameter change enables precise control over which materials are removed, allowing the oxide cap to be eliminated while preserving the polysilicon structures and maintaining device uniformity
2Adaptability or versatility
If an oxide cap layer is used in the integration process, then flash memory cells and MOS transistors can be fabricated in the same chip, but defects are induced and device performance is degraded
Solution Approach 1:
The patent extracts and removes the oxide cap layer that causes defects between control gates. By eliminating this harmful layer through controlled CMP processing, the reliability and performance of the integrated device are improved while maintaining the capability to fabricate both flash memory cells and MOS transistors on the same chip
Solution Approach 2:
The patent converts the potentially harmful presence of the oxide cap layer into a beneficial process feature by using it as a sacrificial layer during CMP. The oxide cap layer is deliberately designed to be removable under specific CMP conditions, allowing it to be cleanly eliminated to improve device performance while the process parameters are optimized to achieve this conversion from harm to benefit
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration of flash memory cells and MOS transistors by reducing cap oxide defects and improving the uniformity of the semiconductor device, addressing the limitations of existing processes.
Implementation Method 1
performing a chemical mechanical polishing (CMP) process to remove the second polysilicon layer, wherein the chemical mechanical polishing process comprises an abrasive of greater than 13% and a remove rate of less than 30 Angstroms/second
Data Source
AI summary
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a memory region and a periphery region; forming a memory cell on the memory region; forming a first polysilicon layer on the periphery region and the memory cell; forming a patterned cap layer on the periphery region; forming a second polysilicon layer on the first polysilicon layer and the patterned cap layer; and performing a chemical mechanical polishing (CMP) process to remove the second polysilicon layer, wherein the chemical mechanical polishing process comprises an abrasive of greater than 13% and a remove rate of less than 30 Angstroms/second.