CMP Recess Compensation via Dual Dielectric Deposition
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The conventional chemical-mechanical planarization (CMP) process in the gate-last semiconductor manufacturing process faces significant challenges in achieving within-in-die uniformity, particularly in the POP CMP step, due to height differences between silicon oxide layers, leading to recesses that can cause short-circuits and processing failures.
Innovation Solution
A method that involves forming a first dielectric isolation layer, planarizing it to expose features, etching to increase recess depth, and then forming a second dielectric isolation layer to refill recesses, followed by a second planarization step to achieve uniformity, using endpoint detection and specific grinding slurries and pads to ensure precise control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional CMP process is used to planarize silicon oxide layer, then the polishing procedure can be completed, but large thickness differences and recesses between polysilicon gates cannot be eliminated, causing uniformity issues
Solution Approach 1:
The CMP process is divided into multiple sequential steps: silicon oxide CMP, silicon nitride CMP, and a compensating deposition step. Each step addresses specific aspects of planarization, with the compensating deposition specifically targeting recess areas to restore uniformity.
Solution Approach 2:
A compensating dielectric layer is deposited beforehand to fill recesses created during CMP processing. This preliminary action prevents the recesses from affecting subsequent processing steps and ensures uniform metal gate formation.
2Manufacturing precision
If silicon oxide CMP is performed on structures with height differences of 1000-1800 Å, then the isolation layer can be planarized, but recesses of about 1000-4000 Å are created between source/drain regions and gate tops
Solution Approach 1:
The recesses created by CMP are converted into a beneficial feature by selectively depositing compensating dielectric material that preferentially fills the recess areas. This transforms the harmful thickness variation into an opportunity for uniformity restoration.
Solution Approach 2:
The deposition parameters are optimized to control the filling behavior of the compensating dielectric layer, ensuring that recess areas are preferentially filled while maintaining appropriate thickness in already-planar regions. The deposition conditions are carefully controlled to achieve the desired compensation effect.
3Reliability
If metal layer is filled in gate trench and recess of silicon oxide layer, then metal gate structures are formed, but metal remains in recess causing short-circuit during metal gate CMP
Solution Approach 1:
The compensating dielectric layer is deposited in advance to fill recesses before metal gate formation. This preliminary action prevents metal from entering recess areas during subsequent processing, eliminating the risk of short-circuits and ensuring uniform metal gate CMP results.
Solution Approach 2:
The compensating dielectric layer acts as an intermediary barrier that prevents metal from accessing recess areas. This intermediate layer selectively blocks metal deposition in recess regions while allowing metal gate formation in appropriate areas, thus preventing short-circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces height differences and compensates for recesses in dielectric isolation layers, improving within-in-die uniformity and preventing short-circuits, thereby enhancing the reliability of the metal gate CMP process and subsequent feature processing.
Implementation Method 1
chemical-mechanical planarization (CMP) process
Implementation Method 2
chemical-mechanical planarization
Implementation Method 3
etching to increase recess depth
Data Source
AI summary
The invention provides a method for improving uniformity of chemical-mechanical planarization process, comprising the steps of: forming features on a substrate; forming a first dielectric isolation layer between the features; planarizing the first dielectric isolation layer until the features are exposed, causing the first dielectric isolation layer between the features to have a recess depth; forming a second dielectric isolation layer on the features and the first dielectric isolation layer, whereby reducing the difference in height between the second dielectric isolation layer between the features and the second dielectric isolation layer on the top of the features; planarizing the second dielectric isolation layer until the features are exposed. According to the method for improving uniformity of chemical-mechanical planarization process of the invention, a dielectric isolation layer is formed again after grinding the dielectric isolation layer on the top of the features, such that the difference in height between the dielectric layer between the features and the dielectric layer on the top of the features is effectively reduced, and the recess of the features is compensated, the within-in-die uniformity is effectively improved.