CMP Resistant Dielectric Structures in Metal Gate Dishing Reduction

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Solution Overview

Problem

The semiconductor industry faces challenges in reducing dishing during the chemical mechanical polish (CMP) process, particularly for high voltage devices with long gate lengths, where severe dishing can result in significant loss of the metal gate structure due to the large continuous metal area, leading to manufacturing inefficiencies.

Innovation Solution

The implementation of dielectric structures with higher CMP resistance properties, embedded within the metal gate structure, which slows down the polishing rate and prevents excessive removal, thereby reducing dishing effects. These dielectric structures are formed from materials like silicon nitride and are strategically placed to withstand the CMP process better than the metal gate, ensuring the metal gate structure remains intact.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If CMP process is performed on metal gate structure, then planarization is achieved, but dishing occurs causing excessive removal of metal gate structure

Engineering Contradiction:

Improveplanarization qualityVSAvoidmetal gate structure loss

Core Design Contradiction:

Manufacturing precisionVSLoss of substance

Solution Approach 1:

The patent applies local quality by forming dielectric structures at specific locations within the metal gate structure. These dielectric structures have different CMP resistance properties compared to the metal gate material, creating localized variations in polishing rate. This ensures that the dielectric regions are removed at different rates than the metal, preventing excessive removal of the metal gate structure while maintaining planarization of the overall surface.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent uses composite materials by combining metal gate material with dielectric structures having different CMP resistance properties. This composite structure allows the metal and dielectric portions to be polished at different rates during CMP, enabling planarization while protecting the metal gate from excessive removal. The dielectric structures act as sacrificial elements that control the polishing dynamics.

Inventive Principle:

Principle #40Composite materials

2Reliability

If large continuous metal area is present in gate structure, then device performance is improved, but dishing during CMP is exacerbated

Engineering Contradiction:

Improvedevice performanceVSAvoiddishing control

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies segmentation by dividing the continuous metal gate structure into regions separated by dielectric structures. These dielectric structures are formed within the metal gate, creating distinct segments that can be polished at different rates. This segmentation prevents the formation of large continuous polished areas that cause dishing, while the metal gate regions between dielectric structures maintain their functional integrity for device performance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces local quality variations by placing dielectric structures with different CMP resistance properties at specific locations within the metal gate. This creates localized differences in polishing behavior, preventing uniform dishing across large continuous metal areas. The dielectric structures act as anchors that control the polishing dynamics in their local regions while preserving the overall metal gate functionality.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The use of CMP resistant dielectric structures embedded in the metal gate structure effectively reduces dishing during the CMP process, maintaining the integrity of the metal gate structure and enhancing manufacturing efficiency by preventing excessive polishing.

Implementation Method 1

dishing during the chemical mechanical polish (CMP) process

Methodology Applied

Scientific EffectChemical mechanical polishing:

Data Source

PatentUS10170334B2Reduction of dishing during chemical mechanical polish of gate structure

Publication Date: 2019.01.01 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device includes a semiconductor substrate, a gate structure and at least one CMP resistant structure. The gate structure is over the semiconductor substrate. The CMP resistant structure is embedded in a top surface of the gate structure. The CMP resistant structure has a CMP resistance property different from a CMP resistance property of the gate structure.