CMP Sacrificial Layer for Flat Metal Alignment Marks
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Solution Overview
Problem
The chemical mechanical polishing (CMP) process in semiconductor manufacturing often results in curved surfaces of metal parts, leading to inaccuracy in alignment marks due to dishing defects, which affect the precision of planarization and device fabrication.
Innovation Solution
A CMP method involving a slurry with an oxidizing agent, catalyst, and abrasive particles is used, along with a CMP sacrificial layer to ensure uniform planarization, preventing dishing and curving of metal layers, and improving alignment mark accuracy by using an organic material that can be easily removed, such as photoresist or BARC, to form alignment marks with precise edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional CMP process is used for planarization, then substrate surface area is reduced and device density is increased, but dishing defects occur causing curved surfaces and reduced alignment mark accuracy
Solution Approach 1:
A sacrificial layer is introduced as an intermediary material between the metal layer and the polishing pad during CMP. This sacrificial layer has different polishing characteristics than the metal layer, allowing it to be preferentially removed or polished at a different rate, thereby compensating for the dishing effect on the metal layer and maintaining its planarity and alignment mark accuracy.
Solution Approach 2:
The invention changes the material parameter of the sacrificial layer to have different chemical or mechanical properties compared to the metal layer. By selecting a sacrificial layer material with appropriate polishing rate characteristics, the CMP process parameters are effectively modified to reduce dishing on the metal layer while maintaining overall planarization.
2Manufacturing precision
If CMP process is performed to achieve planarization, then device controllability is enhanced, but metal layer surfaces become curved reducing fabrication precision
Solution Approach 1:
The sacrificial layer serves as a mediator that absorbs or compensates for the dishing effect during CMP. By controlling the thickness and material properties of this intermediary layer, the metal layer beneath maintains a flatter surface profile after polishing, improving planarization uniformity without developing harmful curvatures.
Solution Approach 2:
The sacrificial layer is applied to the metal layer before the CMP process begins. This preliminary action prepares the surface by creating a protective or compensating layer that will counteract the dishing effect during polishing, ensuring the metal layer emerges with improved surface flatness.
3Productivity
If conventional CMP slurry is used for polishing, then polishing speed is maintained, but alignment mark precision deteriorates due to surface curving
Solution Approach 1:
The sacrificial layer acts as a buffer between the aggressive polishing slurry and the metal layer containing alignment marks. This intermediary protects the metal layer from excessive material removal and surface curving while still allowing the CMP process to proceed at productive speeds, thereby maintaining both polishing efficiency and alignment mark precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves uniform planarization and enhances the accuracy of alignment marks, reducing dishing defects and improving device fabrication precision by ensuring flat and precise edges of metal layers, thereby improving overall semiconductor device manufacturing quality.
Implementation Method 1
a slurry with an oxidizing agent, catalyst, and abrasive particles is used
Implementation Method 2
a slurry with an oxidizing agent, catalyst, and abrasive particles is used
Implementation Method 3
ashing is performed to remove a remaining portion of the organic layer
Data Source
AI summary
In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.