CMP Planarization Using Sacrificial Layer and Selective Slurry
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Solution Overview
Problem
Conventional semiconductor device planarization methods, such as the two-step CMP process, fail to achieve satisfactory planarity, especially for advanced technology nodes like the 15-nm node, due to dishing effects and varying pattern densities, leading to device yield issues and non-planar wafer surfaces.
Innovation Solution
A sacrificial layer is formed with a substantially flat surface using spin-on or FCVD processes, followed by a CMP planarization process with a slurry having uniform polishing selectivity to ensure identical etching rates for all materials, preserving the planarity of the surface across regions with different pattern densities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional two-step CMP process is used for planarization, then the manufacturing process is simple and fast, but the wafer surface exhibits large topography variations and fails to achieve satisfactory planarity
Solution Approach 1:
The planarization process is divided into three distinct steps: (1) a first CMP process to remove excess material, (2) formation of a sacrificial layer to fill凹陷 regions, and (3) a second CMP process to remove the sacrificial layer and achieve final planarity. This segmentation allows each step to address specific topography issues, ultimately achieving better planarity (less than 80 angstroms thickness variation) compared to conventional two-step processes.
2Manufacturing precision
If CMP is performed on wafers with varying pattern densities, then processing can be completed, but dishing effects occur and planarity is compromised
Solution Approach 1:
The sacrificial layer is formed in advance before the second CMP process. This preliminary action fills the凹陷 regions created by varying pattern densities during the first CMP, creating a more uniform surface that prevents dishing effects during subsequent polishing. The sacrificial layer acts as a buffer that compensates for topography variations before final planarization.
3Productivity
If advanced technology nodes like 15-nm are pursued, then device density and integration are improved, but planarization requirements become increasingly difficult to meet
Solution Approach 1:
The sacrificial layer is selectively formed in凹陷 regions where it is most needed, rather than uniformly across the entire wafer. This local application of material addresses the specific planarity issues created by varying pattern densities in different regions of the wafer, allowing advanced technology nodes to achieve the required sub-80-angstrom planarity while maintaining high device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves a significantly planar semiconductor device surface with less than 80 angstroms of thickness variation, improving device yield and compatibility with advanced technology nodes without disrupting existing CMOS process flows.
Implementation Method 1
forming a sacrificial layer over the wafer, wherein the sacrificial layer is formed to have a substantially flat surface profile
Implementation Method 2
performing a CMP planarization process to the wafer, wherein the CMP planarization process removes the sacrificial layer and a portion of the wafer therebelow
Data Source
AI summary
Provided is a method of planarizing a semiconductor device. A dielectric layer is formed over a substrate. A plurality of openings is formed in the dielectric layer. The openings have varying distribution densities. The openings are filled with a metal material. A first chemical-mechanical-polishing (CMP) process is performed to remove portions of the metal material over the dielectric layer. Thereafter, a sacrificial layer is formed over the dielectric layer and the metal material. The sacrificial layer has a planar surface. The sacrificial layer is formed through one of: a spin-on process or a flowable chemical vapor deposition (FCVD) process. A second CMP process is then performed to remove the sacrificial layer and portions of the dielectric layer and the metal material therebelow. The second CMP process uses a slurry configured to have a substantially similar polishing selectivity between the sacrificial layer, the dielectric layer, and the metal material.