CMP Slurry for Ge-SiO2 Composite Planarization
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Solution Overview
Problem
The integration of lattice-mismatched semiconductor materials for high-performance devices, such as CMOS field-effect transistors, faces challenges in planarization due to high dislocation density and surface roughness, particularly when grown on silicon substrates, which requires effective methods to minimize dishing and metallic contamination while maintaining low material removal rates.
Innovation Solution
The use of Chemical Mechanical Polishing (CMP) processes with specific slurry compositions, including additives like H2O2, NaOCl, and Nalco 2360, to planarize Ge-SiO2 composite structures grown in SiO2 trenches on silicon wafers, achieving reduced surface roughness, low dishing, and minimal metallic contamination, while selectively polishing lattice-mismatched crystalline materials relative to insulators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If Chemical Mechanical Polishing (CMP) is used to planarize lattice-mismatched semiconductor materials, then surface roughness is reduced, but dishing and metallic contamination increase
Solution Approach 1:
The patent modifies slurry composition parameters by adding specific chemicals (H2O2, NaOCl, Nalco 2360) to change the polishing chemistry. This resolves the contradiction by enabling effective material removal while controlling dishing and contamination through optimized chemical interactions during CMP
Solution Approach 2:
The patent uses composite slurry formulations combining multiple chemicals (H2O2, NaOCl, Nalco 2360) with colloidal silica. This composite approach addresses the contradiction by creating a synergistic system that achieves planarization while minimizing harmful effects through the combined actions of different chemical components
2Manufacturing precision
If CMP is used to planarize confined mismatched crystalline material, then surface quality is improved, but material removal rate is limited
Solution Approach 1:
The patent adjusts slurry composition parameters including adding H2O2 and NaOCl to enhance material removal rate while maintaining surface quality. The chemical additives modify the polishing reaction kinetics to achieve both goals simultaneously
3Manufacturing precision
If selective polishing is applied to heteroepitaxial regions, then surface uniformity is improved, but process complexity increases
Solution Approach 1:
The patent applies selective polishing by making the slurry chemistry responsive to local material properties. The H2O2 and NaOCl additives create different removal rates for heteroepitaxial regions versus insulators, achieving surface uniformity through localized chemical-mechanical action rather than complex mechanical control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces surface roughness and dishing, achieves selective polishing of Ge over SiO2, and minimizes metallic contamination, making it suitable for device fabrication with improved defect reduction and surface quality.
Implementation Method 1
Chemical Mechanical Polishing (CMP) processes with specific slurry compositions, including additives like H2O2, NaOCl
Implementation Method 2
Chemical Mechanical Polishing (CMP) processes
Implementation Method 3
Chemical Mechanical Polishing (CMP) processes
Data Source
AI summary
A device includes a crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by using a planarization process configured with a selectivity of the crystalline material to the insulator greater than one. In a preferred embodiment, the planarization process uses a composition including abrasive spherical silica, H2O2 and water. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.