Stacked Semiconductor Electrodes With Volumetric Bases After CMP
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving higher integration due to limitations in the bonding process between sensor and circuit boards, which affects the electrical coupling and miniaturization of imaging elements.
Innovation Solution
The semiconductor device incorporates a first and second electrode with protruding and base portions on each substrate, where the base portions have a greater volume than the protruding portions, allowing for effective joining even after planarization processes, enabling secure electrical coupling and higher integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If planarization processes are applied to the abutting surfaces to improve surface flatness, then surface flatness is improved, but the abutting surfaces are partially recessed which reduces bonding reliability
Solution Approach 1:
The patent applies preliminary action by forming the base portions of the electrodes before the planarization process. These base portions are positioned to compensate for the recesses that will occur during CMP (chemical mechanical polishing). By preparing the electrode structure in advance with adequate volume and strategic positioning, the design anticipates and counteracts the future recesses from planarization, ensuring that sufficient bonding area remains after processing.
Solution Approach 2:
The patent employs parameter changes by modifying the volume and spatial distribution of the electrode material. The base portions have greater volume than the protruding portions, creating a volumetric compensation mechanism. This parameter change in electrode geometry allows the system to maintain adequate bonding surface area despite the material removal inherent in planarization processes.
2Reliability
If the electrode volume is increased to compensate for planarization recesses, then bonding reliability is improved, but the overall device size increases
Solution Approach 1:
The patent applies local quality by concentrating the additional electrode volume specifically at the base portions near the bonding interface, rather than uniformly increasing the entire electrode structure. This localized volume enhancement provides the necessary compensation for planarization recesses only where needed at the bonding surface, while keeping other portions of the electrode compact. The base portions serve as localized reservoirs that compensate for surface loss without proportionally increasing overall device volume.
3Productivity
If the imaging element size is reduced to achieve higher integration, then integration density is improved, but the bonding area between substrates is reduced
Solution Approach 1:
The patent transitions from a two-dimensional surface-area-based bonding approach to a three-dimensional volume-based compensation approach. By utilizing the vertical dimension to create base portions with greater volume, the system compensates for reduced bonding area in the horizontal plane. This dimensional transition allows smaller imaging elements to maintain adequate bonding reliability through volumetric electrode design rather than relying solely on lateral surface area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures secure electrical coupling and allows for finer pixel regions with paired coupling terminals, contributing to the miniaturization and higher integration of solid-state imaging units.
Implementation Method 1
a first electrode of the first board and a second electrode of the second board are disposed to be opposed to each other with an insulating thin film interposed in between and then heated to be joined together
Data Source
AI summary
To provide a semiconductor device having a structure suitable for higher integration. This semiconductor device includes: a first semiconductor substrate; and a second semiconductor substrate. The first semiconductor substrate is provided with a first electrode including a first protruding portion and a first base portion. The first protruding portion includes a first abutting surface. The first base portion is linked to the first protruding portion and has volume greater than volume of the first protruding portion. The second semiconductor substrate is provided with a second electrode including a second protruding portion and a second base portion. The second protruding portion includes a second abutting surface that abuts the first abutting surface. The second base portion is linked to the second protruding portion and has volume greater than volume of the second protruding portion. The second semiconductor substrate is stacked on the first semiconductor substrate.