CMP Stop Layer for Gate Height Control in Gate Last Process
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in the semiconductor industry is controlling the gate height during chemical mechanical polishing (CMP) in the gate last process, especially in regions with varying pattern densities, which can lead to uneven gate heights and potential device failure due to overpolishing and damage to active regions.
Innovation Solution
A method involving the formation of a CMP stop layer and an overpolishing process to expose dummy gate structures, where a contact etch stop layer and multiple dielectric layers are used to control the polishing and ensure consistent gate height across different pattern densities, allowing for the subsequent replacement of dummy poly gates with metal gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If CMP is performed on the ILD layer to expose the dummy poly gate for removal, then the gate structure can be accessed for replacement, but the gate height becomes difficult to control in regions with different pattern densities
Solution Approach 1:
A CMP stop layer is introduced as an intermediary layer between the ILD and the dummy gate. This stop layer has different polishing rates compared to the ILD, causing the CMP process to automatically halt when it reaches the stop layer, thereby preventing overpolishing and exposing the dummy gate at the correct height without damaging underlying structures.
Solution Approach 2:
The CMP stop layer is formed in advance before the CMP process that needs to expose the dummy gate. This preliminary action establishes a predetermined polishing endpoint, ensuring that when CMP is performed later, the process will automatically stop at the correct depth to expose the dummy gate without requiring complex real-time monitoring or adjustment.
2Ease of operation
If CMP is performed to expose the dummy gate, then the gate can be removed and replaced with metal gate, but overpolishing may occur causing damage to active regions
Solution Approach 1:
The CMP stop layer serves as a protective cushion layer that is deliberately placed above the dummy gate and active regions. During CMP, this layer absorbs the polishing action and prevents the polishing pad from directly contacting and damaging the underlying active regions, thereby cushioning against potential harm while still allowing the dummy gate to be exposed for removal.
Solution Approach 2:
The CMP stop layer acts as an intermediary protective layer between the CMP process and the sensitive active regions. It mediates the interaction by providing a sacrificial material that can be polished away to expose the dummy gate, but also serves as a barrier that prevents the CMP process from penetrating deeper and causing damage to the active regions beneath.
3Device complexity
If a single dielectric layer is used, then the process is simpler, but it is difficult to control the polishing endpoint to expose dummy gates uniformly across different pattern densities
Solution Approach 1:
The single dielectric layer is segmented into multiple distinct layers: an ILD layer and a CMP stop layer. Each layer has different material properties and polishing rates. This segmentation allows the CMP process to proceed through the ILD layer first, then automatically slow down and stop when reaching the CMP stop layer, enabling uniform exposure of dummy gates across regions with different pattern densities while maintaining relatively simple process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the process window of the CMP process, enabling better control of gate heights and reducing the risk of device failure by minimizing overpolishing and damage, thus enhancing the reliability and performance of semiconductor devices.
Implementation Method 1
performing a chemical mechanical polishing (CMP) on the second dielectric layer that substantially stops at the CMP stop layer; and performing an overpolishing to expose the dummy gate structures
Data Source
AI summary
A method for fabricating a semiconductor device is provided which includes providing a semiconductor substrate, forming a plurality of transistors, each transistor having a dummy gate structure, forming a contact etch stop layer (CESL) over the substrate including the dummy gate structures, forming a first dielectric layer to fill in a portion of each region between adjacent dummy gate structures, forming a chemical mechanical polishing (CMP) stop layer over the CESL and first dielectric layer, forming a second dielectric layer over the CMP stop layer, performing a CMP on the second dielectric layer that substantially stops at the CMP stop layer, and performing an overpolishing to expose the dummy gate structure.