CMP Stop Layer for MRAM Pillar Height Control
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Solution Overview
Problem
The existing methods for forming and exposing magnetic tunnel junction (MTJ) pillars in semiconductor manufacturing face challenges such as difficulty in determining the stopping point of the chemical-mechanical polishing (CMP) process, leading to non-uniformity and potential damage to the pillars, which affects the tunnel magnetoresistance (TMR) values and pillar height control, hindering the creation of higher density arrays for magnetoresistive random access memory (MRAM) devices.
Innovation Solution
A method involving the deposition of layers with different CMP rates, where a high CMP rate material is used to cover the pillars and a low CMP rate material forms valley portions that define a CMP stop height, allowing precise control of the polishing process to prevent damage and ensure uniformity, followed by ion beam etching to expose the top surfaces of the pillars.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP is applied across the wafer to remove insulating layer, then the insulating layer is removed and pillars are exposed, but significant deviation across the wafer in pillar height occurs and pillars may be damaged
Solution Approach 1:
A stop layer is deposited beforehand on the wafer before the insulating layer. This stop layer serves as a predetermined endpoint marker for the CMP process, allowing uniform removal across the entire wafer surface including edge regions. The stop layer prevents over-polishing and pillar damage by providing a clear visual and tactile endpoint, while ensuring consistent pillar height across the wafer.
Solution Approach 2:
The stop layer acts as an intermediary between the CMP polishing pad and the underlying pillars. It absorbs the mechanical action of CMP, providing a uniform polishing surface that protects the pillars from direct contact and potential damage. The stop layer mediates the removal process, ensuring uniform height reduction across the wafer while preventing localized over-etching or pillar damage.
2Productivity
If CMP process progresses through thick insulating layer, then complete removal is achieved, but determining when to stop the CMP process becomes very difficult
Solution Approach 1:
The stop layer is deposited with distinct optical properties (different color or reflectivity) compared to the insulating layer and the underlying pillars. During CMP, as the polishing pad removes material, the exposed stop layer provides a clear visual color change that signals the endpoint. This allows operators to easily detect when the insulating layer has been fully removed and the stop layer is exposed, eliminating difficulty in endpoint detection.
3Ease of operation
If CMP is used to expose MTJ pillars, then pillars can be exposed, but non-uniform polishing creates resistance uniformity issues and can cause pillar damage
Solution Approach 1:
The stop layer serves as a protective intermediary that ensures uniform polishing across the wafer. By providing a consistent polishing surface with uniform mechanical properties, it mediates the CMP process to remove material evenly from all pillar regions. This uniformity prevents variations in pillar height that would otherwise cause resistance uniformity issues, while still enabling complete pillar exposure when the stop layer is reached.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves consistent CMP across the wafer, reduces the risk of pillar damage, and improves TMR values, enabling the production of MRAM devices with higher area density and precise pillar heights, resulting in improved resistance-area and resistance-readout signals.
Implementation Method 1
chemical-mechanical polishing the plurality of MTJ pillar bumps
Implementation Method 2
ion beam etching to expose the top surfaces of the pillars
Data Source
AI summary
Described embodiments can be used in semiconductor manufacturing and employ materials with high and low polish rates to help determine a precise polish end point that is consistent throughout a wafer and that can cease polishing prior to damaging semiconductor elements. The height of the low polish rate material between the semiconductor elements is used as the polishing endpoint. Because the low polish rate material slows down the polishing process, it is easy to determine an end point and avoid damage to the semiconductor elements. An additional or alternative etch end point can be a thin layer of material that provides a very clear spectroscopy signal when it has been exposed, allowing the etch process to cease.


