CMP Stopping Layer for TSV Integration
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Solution Overview
Problem
The existing Chemical Mechanical Polishing (CMP) process for Through Silicon Vias (TSVs) has a narrow process window due to non-selective removal of conductive and barrier materials, leading to potential damage to the dielectric stack and increased risk of shorts, especially when dealing with high aspect ratio vias and non-uniformities in deposition.
Innovation Solution
A common CMP stopping layer is deposited on the dielectric top layer before etching and filling, allowing it to control both the CMP steps for contact vias and TSVs, ensuring precise removal of overburden without excessive consumption of dielectric material, thus expanding the process window and preventing damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP process is used to remove overburden of barrier and conductive material after TSV filling, then the conductive material and barrier material are removed from the surface, but the dielectric material is also consumed excessively causing damage to underlying structures
Solution Approach 1:
A dedicated CMP stop layer is introduced as an intermediary between the dielectric stack and the overburden materials. This stop layer has selective etch characteristics that allow CMP to remove barrier and conductive materials while automatically halting before significantly eroding the dielectric stack, thus protecting underlying structures.
Solution Approach 2:
The CMP stop layer is deposited in advance before the barrier and conductive material layers are formed. This preliminary action ensures that when CMP is performed later to remove overburden, the stop layer is already in position to protect the dielectric stack from excessive consumption.
2Reliability
If a thick barrier layer is deposited to ensure continuous coverage on high aspect ratio vias, then the barrier coverage is improved, but the CMP process window becomes narrower due to non-selective removal
Solution Approach 1:
The CMP stop layer serves as a mediator that decouples the barrier layer thickness requirement from the CMP process control. By providing this intermediate layer with distinct etch selectivity, the system can use thicker barrier layers for reliable coverage without proportionally increasing CMP process risk, as the stop layer absorbs the variability.
Solution Approach 2:
The invention changes the material composition and thickness parameters of the CMP stop layer to achieve optimal etch selectivity. By carefully controlling the stop layer's physical and chemical properties, the CMP process window is expanded, allowing thicker barrier layers to be used while maintaining process control.
3Manufacturing precision
If over-polish is applied to compensate for non-uniformities in CMP, then non-uniformity issues are addressed, but the dielectric stack is strongly affected with loss of several tenths of percent of total thickness
Solution Approach 1:
The CMP stop layer acts as a sacrificial intermediary that absorbs the impact of over-polish operations. Since the stop layer is specifically designed with etch selectivity, it can be removed uniformly during over-polish without significantly affecting the underlying dielectric stack, thus maintaining material integrity.
Solution Approach 2:
The CMP stop layer provides beforehand cushioning against the harmful effects of over-polish. By positioning this protective layer before the dielectric stack, the system is pre-cushioned against excessive material removal, allowing standard over-polish procedures to be performed safely.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the CMP process window, allowing for a 10-20% over-polish without damaging the dielectric stack, reduces contamination risks, and maintains the integrity of the semiconductor device, improving the reliability of TSV integration.
Implementation Method 1
by applying Chemical Mechanical Polishing techniques (CMP)
Implementation Method 2
A common CMP stopping layer is deposited on the dielectric top layer before etching and filling, allowing it to control both the CMP steps
Data Source
Figure 1~2
Figure 3A~3B
Figure 4A~4H
AI summary
The present invention is related to method for producing a semiconductor device comprising the steps of: - providing a semiconductor substrate (1), comprising active components on the surface of said substrate, - depositing a top layer (2) of dielectric material on the surface of said substrate or on other dielectric layers present on said surface, - etching at least one first opening (7) at least through said top layer, filling said opening(s) at least with a first conductive material (8), and performing a first CMP step, to form said first conductive structures (3,26), - etching at least one second opening (13) at least through said top layer, filling said opening(s) at least with a second conductive material (10), and performing a second CMP step, to form said second conductive structures (4,24), wherein the method comprises the step of depositing a common CMP stopping layer (5,25) on said dielectric top layer, before the steps of etching and filling said first opening(s), so that said same CMP stopping layer is used for stopping the CMP process after filling of the first opening(s) as well as the CMP process after filling of the second opening(s). The invention is equally related to devices obtainable by the method of the invention.