CMP Surface Conversion for Uniform Dielectric Planarization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Chemical mechanical polishing (CMP) processes face challenges in achieving perfect planarization, especially when dealing with extreme topologies and varying underlying structures across different areas of a semiconductor chip, leading to non-uniformity and the need to stop the process prematurely to avoid over-etching.
Innovation Solution
A method involving the deposition of a barrier layer, a liner layer, and an overburden layer, followed by a series of CMP and etch processes, including selective and non-selective CMP steps, and surface conversion, to planarize the dielectric layer without relying on underlying topology, ensuring uniformity across the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP process continues until perfect planarization is achieved, then surface flatness is improved, but risk of over-etching and removing underlying layers increases
Solution Approach 1:
A stop layer is deposited beforehand between the planarization layer and underlying layers. This preliminary action creates a protective barrier that allows the CMP process to continue until the stop layer is exposed, ensuring perfect planarization without risk of removing underlying layers. The stop layer acts as a predetermined endpoint marker for the polishing process.
Solution Approach 2:
The stop layer serves as an intermediary layer between the planarization layer and underlying structures. It mediates the CMP process by being selectively removed to expose a predetermined pattern, allowing the polishing to proceed uniformly across the entire wafer surface without compromising underlying layers. This intermediary enables continued polishing while protecting critical underlying structures.
2Reliability
If CMP process stops before perfect planarization to avoid over-etching, then layer integrity is preserved, but surface uniformity deteriorates
Solution Approach 1:
The stop layer is deposited in advance with a predetermined pattern that defines the polishing endpoint. This preliminary configuration allows the CMP process to proceed uniformly across the entire wafer surface, achieving perfect planarization without requiring premature termination. The predetermined pattern ensures consistent removal across all areas, eliminating surface uniformity issues.
Solution Approach 2:
The introduction of the stop layer changes the removal parameter of the CMP process. By having a layer with different etch selectivity than the planarization layer, the process can continue longer and remove more material uniformly across the wafer, achieving better surface uniformity while the stop layer protects underlying structures from over-removal.
3Device complexity
If timed polish is used to control CMP duration, then process simplicity is maintained, but planarization quality deteriorates due to extreme topology variations
Solution Approach 1:
The timed polish mechanical control system is replaced with a chemical selectivity-based control system using the stop layer. Instead of relying on time-based mechanical polishing which cannot adapt to topology variations, the process uses chemical etch selectivity where the stop layer is selectively removed to expose a predetermined pattern. This substitution provides automatic adaptation to varying topologies across the wafer, achieving high planarization quality while maintaining process simplicity through a single extended polishing step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances planarization and within-chip uniformity by allowing precise control over the CMP process, avoiding the limitations of prior art methods that depend on timed polishes or resource-intensive processes, resulting in a more consistent and reliable planarized surface.
Implementation Method 1
A barrier layer is deposited over a planarization layer. Next, a liner layer is deposited on the barrier layer. An overburden layer is deposited on the liner layer.
Implementation Method 2
A barrier layer is deposited over a planarization layer. Next, a liner layer is deposited on the barrier layer. An overburden layer is deposited on the liner layer.
Implementation Method 3
A first chemical mechanical polishing (CMP) process is performed on the overburden layer.
Implementation Method 4
A surface conversion process is performed on uncovered portions of a top surface of the planarization layer which are not protected by the polished overburden layer.
Implementation Method 5
A first wet etch is performed of the planarization layer. In embodiments, the first wet etch is selective to metal overburden layer as compared to the planarization layer.
Implementation Method 6
A second wet etch is performed removing the liner layer, the diffusion barrier layer and the metal overburden layer. In embodiments, the second wet etch is selective to the planarization layer as compared to the overburden layer.
Data Source
AI summary
A method for fabricating a planarized planarization layer for an integrated circuit device is described. A barrier layer is deposited over a planarization layer. Next, a liner layer is deposited on the barrier layer. An overburden layer is deposited on the liner layer. A first chemical mechanical polishing (CMP) process is performed on the overburden layer. A surface conversion process is performed on uncovered portions of a top surface of the planarization layer which are not protected by the polished overburden layer. A first wet etch is performed of the planarization layer. In embodiments, the first wet etch is selective to metal overburden layer as compared to the planarization layer. A second wet etch is performed removing the liner layer, the diffusion barrier layer and the metal overburden layer. In embodiments, the second wet etch is selective to the planarization layer as compared to the overburden layer.