CMP Surface Leveling in Integrated Circuit Structures
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Solution Overview
Problem
In integrated circuit fabrication, the chemical mechanical polishing process often results in uneven top surfaces of dielectric and conductive layers due to differing removal rates, leading to reliability issues from peeling between layers.
Innovation Solution
A method involving the formation of a dielectric layer, a barrier layer, and a liner, followed by chemical mechanical polishing with a slurry that removes these layers at distinct rates, and the subsequent formation of a conductive cap, with inline control systems providing feedback for precise polishing adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing removes dielectric and conductive layers at different rates, then surface leveling occurs, but peeling between layers occurs due to stress
Solution Approach 1:
The barrier layer serves as a cushioning element that absorbs and distributes stress during the polishing process. By controlling the removal rate of this barrier layer, the patent prevents stress concentration that would otherwise cause peeling between the dielectric and conductive layers
Solution Approach 2:
The patent changes polishing parameters between stages: the first polishing stage uses parameters optimized for removing both dielectric and conductive materials, while the second stage uses different parameters optimized for selective dielectric removal. This parameter change allows surface leveling without causing layer peeling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures reliable integrated circuit structures by eliminating peeling areas and achieving precise surface leveling, enhancing the structural integrity and reliability of the circuits.
Implementation Method 1
a process, such as a chemical mechanical polishing (CMP) process, for example, results in a removal of at least some of at least one of the dielectric layer, the conductive structure, the barrier layer, or the liner
Data Source
AI summary
One or more integrated circuit structures and techniques for forming such integrated circuit structures are provided. The integrated circuit structures comprise a conductive structure that is formed within a trench in a dielectric layer on a substrate. The conductive structure is formed over a barrier layer formed within the trench, or the conductive structure is formed over a liner formed over the barrier layer. At least some of the dielectric layer, the barrier layer, the liner and the conductive structure are removed, for example, by chemical mechanical polishing, such that a step height exists between a top surface of the substrate and a top surface of the dielectric layer. Removing these layers in this manner removes areas where undesired interlayer peeling is likely to occur. A conductive cap is formed on the conductive structure.