Collective Memory Scheduling Engine for Multi-Core Processors
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Solution Overview
Problem
High-performance computing algorithms, such as climate modeling and heat transfer simulations, are constrained by main memory bandwidth due to large data operations, leading to inefficient use of computing elements and increased energy consumption.
Innovation Solution
A collective memory scheduling (CMS) engine coordinates data transfers between multiple-core processors and memory, ensuring sequential reading and writing of data in memory address order, thereby optimizing memory bandwidth and reducing energy usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfers are coordinated sequentially in memory address order, then memory bandwidth utilization is improved, but device complexity increases due to the control unit and mapping mechanisms
Solution Approach 1:
A control unit is introduced as an intermediary between processor cores and memory to coordinate data transfers. The control unit receives trigger packets from processor cores, generates mappings between memory address ranges and processor cores, and coordinates sequential reading/writing of data lines from memory to processors, thereby improving memory bandwidth utilization despite the added complexity.
2Loss of energy
If collective memory transfers are implemented across multiple processor cores, then energy consumption is reduced, but the difficulty of coordinating data transfers increases
Solution Approach 1:
The control unit implements feedback mechanisms by receiving trigger packets from processor cores indicating their readiness state, observing memory access patterns, and adjusting the coordination of data transfers accordingly. This feedback enables efficient energy utilization while managing the complexity of multi-core coordination through adaptive control.
3Adaptability or versatility
If mapping between memory address ranges and processor cores is generated dynamically, then adaptability to different data access patterns is improved, but processing time increases
Solution Approach 1:
The control unit generates mappings between memory address ranges and processor cores in advance based on observed memory access patterns. By performing preliminary mapping generation and storing it for future use, the system achieves adaptability to different data access patterns while minimizing the time loss during actual data transfer operations.
Data Source
AI summary
This disclosure provides systems, methods, and apparatus for collective memory transfers. A control unit may be configured to coordinate a transfer of data between a memory and processor cores. For a read data transfer operation, the control unit may receive a trigger packet identifying a read data transfer operation and identifying a first plurality of data lines based on data values included in the trigger packet. The control unit may read the first plurality of data lines from the memory sequentially and send a second plurality of data lines to the processor cores. For a write data transfer operation, the control unit may send a request for at least one data line to a plurality of processor cores, may receive and reorder the requested data lines, and may write the data lines to a memory. The control unit may determine a mapping between processor cores and the memory.