CMU Hardware Clock Control for Fast IP Block Wake and Sleep
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Solution Overview
Problem
The control of clock sources in a clock management unit (CMU) of a semiconductor device is typically slower when performed using software compared to hardware, leading to inefficiencies in managing clock signals for intellectual property (IP) blocks.
Innovation Solution
Incorporating a first and second clock control circuit within the CMU that can receive clock requests from IP blocks and control corresponding clock sources, along with a CMU controller that manages these circuits and receives control commands from a power management unit (PMU), enabling hardware-wise control of clock sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If software is used to control clock sources in the CMU, then the control function can be implemented, but the control speed becomes slower
Solution Approach 1:
The patent segments the clock control function into two independent parts: a software-controlled multiplexer for high-level clock source selection and hardware-controlled clock dividing/gating circuits for low-level clock signal management. This segmentation allows each component to operate at its optimal control level, with hardware providing fast response for critical clock signals while software maintains flexibility for system-level coordination.
Solution Approach 2:
The patent introduces a hardware intermediary mechanism (hardware control circuit) between the software and the clock sources. This intermediary receives control signals from the software through a control signal generation unit and directly manipulates the clock signals through hardware circuits, thereby achieving both software flexibility and hardware speed.
2Speed
If hardware control is used for clock sources, then the control speed increases, but the device complexity increases
Solution Approach 1:
The patent divides the clock control system into distinct functional modules: a multiplexer for clock source selection, clock dividing circuits for frequency division, and clock gating circuits for signal enablement/disability. Each module is independently controlled by dedicated control signals, allowing hardware-speed control while maintaining modular simplicity and reducing overall system complexity through functional decomposition.
Solution Approach 2:
The hardware control circuits are designed to automatically respond to control signals without requiring complex software intervention. The multiplexer, clock dividing circuits, and clock gating circuits operate autonomously based on incoming control signals, reducing the burden on the software system and simplifying the control architecture while maintaining high-speed operation.
Data Source
AI summary
A clock management unit (CMU) includes a first clock control circuit controlling a first clock source, a second clock control circuit sending a first clock request to the first clock control circuit in response to an intellectual property (IP) block clock request from an IP block and controlling a second clock source, and a CMU controller. The second clock control circuit receives a clock signal from the first clock source. A power management unit (PMU) sends a PMU clock request to the CMU controller. The CMU provides the clock signal to the IP block in response to the PMU clock request.