CMUT Electrode Encapsulation to Prevent Polishing-Induced Breakdown
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Solution Overview
Problem
The 'patterning last' process in CMUT production exposes the bottom electrode, leading to high risk of sidewall or corner metal exposure during chemical-mechanical polishing, resulting in charging and premature breakdown, especially during high voltage and/or high frequency operation.
Innovation Solution
A 'patterning first' process is employed where the bottom electrode is patterned before dielectric films, fully encapsulating it with multiple dielectric layers to protect the sidewalls and corners, reducing the risk of exposure and breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the 'patterning last' process is used to simplify manufacturing, then the manufacturing process is easier, but the bottom electrode is exposed leading to high risk of sidewall or corner metal exposure during chemical-mechanical polishing
Solution Approach 1:
The bottom electrode is patterned in advance before the final dielectric layers are deposited, allowing it to be fully encapsulated by subsequent dielectric layers. This preliminary patterning action prevents metal exposure during chemical-mechanical polishing while maintaining manufacturing feasibility through a modified process sequence
2Reliability
If the bottom electrode is fully encapsulated with multiple dielectric layers, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The dielectric structure is divided into multiple discrete layers (first dielectric layer, second dielectric layer, third dielectric layer) with each layer serving a specific protective function. This segmentation provides comprehensive electrode protection while allowing for systematic process control and quality management
3Ease of manufacture
If the bottom electrode is exposed during chemical-mechanical polishing, then the manufacturing process is simpler, but charging and premature breakdown occur during high voltage and high frequency operation
Solution Approach 1:
Multiple dielectric layers are deposited beforehand to completely cover and protect the bottom electrode before chemical-mechanical polishing occurs. This protective cushioning prevents metal exposure during polishing and eliminates the risk of charging and premature breakdown during high voltage and high frequency operation
Data Source
AI summary
A semiconductor device and method of manufacturing the device that includes a capacitive micromachined ultrasonic transducer (CMUT). The CMUT includes an integrated circuit substrate, and a sensing electrode positioned on the integrated substrate. The sensing electrode includes a sidewall that forms a wall of an isolation trench adjacent to the sensing electrode, and is patterned before covering dielectric layers are deposited. After patterning of the sensing electrode, one or more dielectric layers are patterned, with one dielectric layer patterned on the sensing electrode and sidewall, and which has a thickness corresponding to the surface roughness of the sensing electrode. The CMUT further includes a membrane positioned above the sensing electrode forming a cavity therein.