CMUT Device Interconnect Formation via Dielectric Thickness Reduction
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Solution Overview
Problem
Conventional CMUT device manufacturing faces challenges in achieving high yields and cost-effectiveness, particularly when producing devices with thick membrane layers and large diameters, due to difficulties in etching through thick dielectric layers and forming interconnects with favorable aspect ratios for low-frequency operation.
Innovation Solution
A method is introduced to reduce the thickness of the dielectric layer stack in the interconnect region by partial etching, allowing for the formation of trenches with reduced aspect ratios, which facilitates effective lining or filling with conductive material, thereby improving interconnect quality and manufacturing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the membrane diameter is increased to enable low-frequency operation, then the operating frequency range is improved, but the membrane thickness and overall dielectric layer stack thickness increase, making etching and interconnect formation difficult
Solution Approach 1:
The device is divided into two distinct regions: a CMUT cell region with thick dielectric layers for low-frequency operation, and an interconnect region with reduced dielectric thickness for easy interconnect formation. This spatial segmentation allows each region to be optimized independently for its specific function.
Solution Approach 2:
Different regions of the dielectric layer stack have different thicknesses tailored to their specific requirements. The CMUT cell region maintains thick dielectric layers (1-2 microns or more) for proper membrane operation at low frequencies, while the interconnect region has reduced thickness (less than 1 micron) to facilitate trench etching and metal filling.
2Strength
If the dielectric layer stack thickness is increased to support thick membrane layers, then the membrane structural integrity is improved, but the aspect ratio of interconnect trenches becomes unfavorable, reducing manufacturing yield
Solution Approach 1:
The dielectric layer stack is segmented into regions of different thicknesses. The CMUT cell region retains the full thick dielectric stack to support large-diameter membranes for low-frequency operation, while the interconnect region has selectively removed dielectric material to create a thinner section that enables favorable aspect ratios for trench etching and metal interconnect formation.
Solution Approach 2:
The dielectric layer stack thickness is reduced in the interconnect region before trench etching and interconnect formation. This preliminary thinning action ensures that when trenches are subsequently etched and filled with metal, the aspect ratio is favorable, leading to complete filling and high manufacturing yield.
3Adaptability or versatility
If conventional fabrication methods are used for thick dielectric layers, then the membrane thickness can be increased for low-frequency operation, but the interconnect region requires excessive etching time and resist consumption, reducing productivity
Solution Approach 1:
The fabrication process is segmented so that the CMUT cell region undergoes complete processing with thick dielectric layers, while the interconnect region receives selective additional processing to reduce dielectric thickness. This allows the device to achieve both thick membranes for low-frequency operation and efficient interconnect formation without excessive etching time.
Solution Approach 2:
The dielectric layer stack is processed differently in different regions: the CMUT cell region maintains thick dielectric layers for proper membrane operation, while the interconnect region has locally reduced thickness to enable fast, efficient interconnect formation with minimal etching time and resist consumption.
Data Source
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AI summary
Disclosed is a method of manufacturing a device (1) comprising a plurality of micro-machined ultrasonic transducer cells (100) in a first region (10) on a substrate (30) and a plurality of interconnects (200) in a second region (20) on said substrate, each of said cells comprising a first electrode (100) separated by a cavity (130) from a second electrode (120) supported by a membrane (140), the method comprising forming a dielectric layer stack (11, 13, 15, 17) over the substrate, said dielectric layer stack defining the respective membranes of the micro-machined ultrasonic transducers in the first region; reducing the thickness of the dielectric layer stack in the second region by partially etching away the dielectric layer stack in the second region; etching a plurality of trenches (22) in the reduced thickness portion of the dielectric layer stack, each of said trenches exposing a conductive contact (210) in the second region; and filling said trenches with a conductive material. A device manufactured in accordance with this method and an apparatus including the device are also disclosed.