CNFET Logic Stage Pairing for Noise Margin
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Solution Overview
Problem
Carbon nanotube field-effect transistors (CNFETs) face challenges due to the presence of metallic carbon nanotubes (m-CNTs), which lead to increased leakage power and degraded noise immunity, making it difficult to achieve the desired energy efficiency and noise margin in digital VLSI circuits, as existing techniques fail to achieve the required semiconducting CNT purity.
Innovation Solution
The DREAM system designs integrated circuits by computing the static noise margin (SNM) for pairs of logic stages with m-CNTs and selecting only those with SNM above a threshold, allowing for circuit design optimization that mitigates the impact of m-CNTs without additional processing steps, thereby relaxing the purity requirements and improving noise resilience.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional CNT synthesis is used, then manufacturing simplicity is maintained, but semiconducting CNT purity is insufficient (only about 66% achieved)
Solution Approach 1:
The patent extracts and removes metallic CNTs from the mixture through selective breakdown processes, separating them from semiconducting CNTs. This extraction approach allows retention of the simple synthesis method while achieving higher purity through post-synthesis separation rather than attempting perfect separation during synthesis.
Solution Approach 2:
The patent changes physical or chemical parameters (such as applying high voltages for electrical breakdown, or using chemical etchants) to selectively remove metallic CNTs. By changing these parameters during post-processing, the system achieves high purity without changing the fundamental simplicity of the initial CNT synthesis process.
2Manufacturing precision
If additional processing steps are applied to remove m-CNTs, then semiconducting CNT purity is improved, but energy-delay product penalties increase
Solution Approach 1:
The patent applies partial processing actions that are sufficient to achieve the required purity level without excessive processing. By carefully controlling the breakdown process to remove only the necessary metallic CNTs and avoiding over-processing, the system achieves high purity while minimizing energy consumption and delay penalties.
Solution Approach 2:
The patent optimizes processing parameters (such as voltage levels for electrical breakdown or chemical concentration for etching) to achieve maximum purity with minimum energy input. By finding the optimal parameter settings, the system removes metallic CNTs effectively while avoiding excessive energy consumption that would increase the energy-delay product.
3Loss of energy
If high semiconducting CNT purity is achieved through existing techniques, then leakage power is reduced, but noise margin constraints are still not satisfied for VLSI circuits
Solution Approach 1:
The patent extracts and removes metallic CNTs through selective breakdown processes, separating them from semiconducting CNTs. This extraction approach allows retention of the simple synthesis method while achieving higher purity through post-synthesis separation rather than attempting perfect separation during synthesis.
Solution Approach 2:
The patent introduces intermediary processing steps (such as electrical breakdown at high voltages or chemical etching processes) that act as mediators between the raw CNT mixture and the final high-purity semiconducting CNT structure. These intermediary steps selectively remove metallic CNTs without damaging semiconducting ones, achieving both low leakage power and sufficient noise margin.
Data Source
AI summary
System and methods to generate a circuit design for an integrated circuit using only allowable pairs of connected logic stages. The allowable pairs of connected logic stages are those pairs of connected logic stages with a static noise margin (SNM) above an SNM threshold. Also presented is a 16-bit microprocessor made entirely from carbon nanotube field effect transistors (CNFET) having such allowable pair of connected logic stages.