Carbon Nanotube Ternary SRAM Cell for Low Standby Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Ternary SRAM cells using carbon nanotube field effect transistors (CNFETs) face issues with high DC power loss when storing logic '1', half-select problems affecting unselected memory nodes, and low static noise margin and stability due to read-disturb issues.
Innovation Solution
A carbon nanotube ternary SRAM cell design with specific configurations of P-type and N-type CNFETs, including read and write transmission gates, and a read buffer, which reduces DC paths during logic '1' storage, isolates memory nodes from bit lines during read operations, and enhances static noise margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional ternary SRAM cell configuration is used, then memory capacity is improved, but DC power loss increases due to two DC paths when storing logic '1'
Solution Approach 1:
The patent extracts and removes one of the two DC paths that exist in traditional ternary SRAM cells when storing logic '1'. By modifying the transistor configuration and connectivity, the design eliminates the redundant current path, thereby reducing DC power loss while preserving the ternary storage capability.
Solution Approach 2:
The patent changes the electrical parameters of the cell by introducing transmission gates with specific on/off characteristics and adjusting transistor sizing ratios. These parameter changes optimize the current flow paths to minimize DC power consumption while maintaining the ability to store three distinct logic states.
2Quantity of substance
If traditional ternary SRAM cell configuration is used, then memory capacity is improved, but half-select problem affects unselected memory nodes
Solution Approach 1:
The patent introduces transmission gates as intermediary elements between the bit lines and the memory cell cores. These transmission gates act as controlled switches that isolate unselected memory nodes from the bit lines during read and write operations, preventing half-select disturbances while allowing full access to selected cells.
Solution Approach 2:
The patent employs dynamically controlled transmission gates that switch between conductive and high-impedance states based on the selection signals. This dynamic control ensures that only selected memory nodes are connected to the bit lines during operations, eliminating half-select problems while maintaining high-speed access.
3Use of energy by stationary object
If novel ternary SRAM cell configuration is used, then standby power is reduced, but static noise margin decreases due to read-disturb problem
Solution Approach 1:
The patent uses transmission gates as intermediary isolation elements during read operations. These gates prevent direct disturbance of the stored data by controlling the coupling between the bit lines and the memory nodes, thereby maintaining high static noise margin while achieving low standby power through optimized transistor configurations.
Solution Approach 2:
The patent implements protective circuitry and isolation mechanisms that cushion the memory nodes from read-disturb effects before they can cause errors. The transmission gates and carefully designed transistor ratios provide preemptive protection, ensuring data integrity is maintained even during frequent read operations.
Data Source
AI summary
A carbon nanotube ternary SRAM cell with an improved stability and low standby power comprises a write bit line, a read bit line, a column select bit line, an inverted column select bit line, a write word line, an inverted write word line, a read word line, an inverted read word line, a first P-type CNFET, a second P-type CNFET, a third P-type CNFET, a fourth P-type CNFET, a fifth P-type CNFET, a sixth P-type CNFET, a seventh P-type CNFET, an eighth P-type CNFET, a ninth P-type CNFET, a first N-type CNFET, a second N-type CNFET, a third N-type CNFET, a fourth N-type CNFET, a fifth N-type CNFET, a sixth N-type CNFET, a seventh CNFET, an eighth N-type CNFET and a ninth N-type CNFET. The carbon nanotube ternary SRAM cell has the advantages of being lower in power consumption, capable of solving the half-select problem and the read-disturb problem and high in static noise margin.