Compute-Near-Memory Architecture for SAR Cache Hit Optimization

The patent merges processing units with memory structures by implementing compute-near-memory architectures where processors are integrated directly into or adjacent to memory devices. This allows data processing to occur at the memory location itself, eliminating the need for separate data transfer operations between independent processors and memory, thereby reducing latency and improving processing performance.

The patent introduces a new architectural dimension by moving computation from a centralized processor to the memory dimension itself. Through in-memory computing and memory-embedded processing units, the system adds a spatial dimension where computation occurs alongside data storage, transforming the traditional sequential data transfer model into a parallel in-situ processing model that reduces time loss.

The patent combines memory and processing functions into integrated memory devices with embedded compute units. This merging eliminates energy-consuming data transfer operations over external buses by performing computations directly within the memory structure, thereby maintaining processing capacity while significantly reducing energy loss associated with data movement.

The patent enables memory devices to perform computational operations on their own stored data without requiring external processor intervention. Through in-memory computing capabilities, the memory system serves itself by executing arithmetic and logic operations directly on resident data, eliminating the energy expenditure required for data transfer to and from separate processors.